Chihiro Matsui

48 papers A 1C 8Journal 20Unranked 19
YearRankTypeTitle / Venue / Authors
2026 J jnl
ReRAM Resistance Design of LRS and HRS for Ultrahigh-Capacity Digital Memory and Analog Computation-in-Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chihiro Matsui, Ayumu Yamada, Naoko Misawa, Ken Takeuchi
2025 J jnl
4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation.
CoRR
Fuyuki Kihara, Seiji Uenohara, Satoshi Awamura, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025 — conf
Bayesian Neural Network Realization by Random Telegraph Noise in 40nm TaOX ReRAM CiM.
IMW
Junnosuke Furukawa, Koki Shibata, Kenshin Yamauchi, Naoko Misawa, Satoshi Awamura, Chihiro Matsui, Ken Takeuchi
2025 — conf
Conductance Variation-Assisted Adversarial Attack Robustness on 40nm TaOx-based ReRAM CiM.
IRPS
Kenshin Yamauchi, Naoko Misawa, Satoshi Awamura, Masahiro Morimoto, Chihiro Matsui, Ken Takeuchi
2025 — conf
Hybrid ReRAM-NMC & SRAM-CiM Matrix Multiplication for Large Language Model.
COOL CHIPS
Tao Wang, Daqi Lin, Kenshin Yamauchi, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025 J jnl
RGB-Event Multi-Modal NV-CiM to Detect Object by Mapping-Oriented Enhanced-Feature Pyramid Network with Mapping-Aware Group Convolution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuya Ichikawa, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025 — conf
Read Voltage Dependency of Random Telegraph Noise in the Intermediate State of TaOx-based ReRAM.
IRPS
Kenshin Yamauchi, Naoko Misawa, Hisashi Shima, Yasuhisa Naitoh, Hiroyuki Akinaga, Chihiro Matsui, Ken Takeuchi
2025 J jnl
Signed Approximate Adder Tree and Quantization- and Bit-Pruning-Aware Training for Digital Computation-in-Memory.
IEICE Trans. Electron.
Daqi Lin, Tao Wang, Adil Padiyal, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025 — conf
Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices.
ASP-DAC
Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi
2025 C conf
VaLI: Variability-aware Fine-tuning with Low-rank Adapter and Iterative Training for ReRAM Computation-in-Memory.
ISCAS
Tao Wang, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2024 J jnl
3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing.
IEICE Trans. Electron.
Fuyuki Kihara, Chihiro Matsui, Ken Takeuchi
2024 J jnl
Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern Classifier.
IEICE Trans. Electron.
Ayumu Yamada, Zhiyuan Huang, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2024 — conf
Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers.
IMW
Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi
2024 J jnl
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
2024 J jnl
REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night.
IEICE Trans. Electron.
Yuya Ichikawa, Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023 J jnl
Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chihiro Matsui, Ken Takeuchi
2023 A conf
LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory.
ICCAD
Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023 — conf
ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset.
IRPS
Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023 — conf
Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance.
IMW
Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023 J jnl
Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM.
IEICE Trans. Electron.
Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi
2022 C conf
Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing.
ISCAS
Naoko Misawa, Kenta Taoka, Chihiro Matsui, Ken Takeuchi
2022 C conf
Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation.
ISCAS
Shinsei Yoshikiyo, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2022 — conf
Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation.
IMW
Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi
2022 — conf
Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM.
IMW
Yuya Ichikawa, Akira Goda, Chihiro Matsui, Ken Takeuchi
2022 C conf
Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing.
ISCAS
Chihiro Matsui, Eitaro Kobayashi, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
2021 C conf
BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads.
ISCAS
Mamoru Fukuchi, Shun Suzuki, Kyosuke Maeda, Chihiro Matsui, Ken Takeuchi
2021 — conf
Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing.
VLSI Circuits
Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
2021 — conf
Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory.
IMW
Kenta Taoka, Naoko Misawa, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi
2020 J jnl
Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs).
IEICE Trans. Electron.
Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi
2020 — conf
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers.
VLSI-DAT
Yoshiki Kakuta, Reika Kinoshita, Hiroshi Kinoshita, Chihiro Matsui, Ken Takeuchi
2020 J jnl
System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs.
IEICE Trans. Electron.
Mamoru Fukuchi, Chihiro Matsui, Ken Takeuchi
2020 — conf
Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance.
ASP-DAC
Reika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi
2019 — conf
Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories.
ASP-DAC
Chihiro Matsui, Ken Takeuchi
2019 J jnl
Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Chihiro Matsui, Ken Takeuchi
2019 C conf
Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories.
ISCAS
Chihiro Matsui, Ken Takeuchi
2019 J jnl
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage.
Integr.
Chihiro Matsui, Ken Takeuchi
2018 C conf
20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD.
ISCAS
Mamoru Fukuchi, Yukiya Sakaki, Chihiro Matsui, Ken Takeuchi
2018 C conf
3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage.
ISCAS
Chihiro Matsui, Ken Takeuchi
2018 J jnl
Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size.
IEICE Trans. Electron.
Hirofumi Takishita, Yutaka Adachi, Chihiro Matsui, Ken Takeuchi
2018 — conf
Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs.
VLSI-DAT
Yutaka Adachi, Chihiro Matsui, Ken Takeuchi
2018 — conf
Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM.
NVMTS
Reika Kinoshita, Chihiro Matsui, Shinpei Matsuda, Yutaka Adachi, Ken Takeuchi
2018 — conf
Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature.
NVMTS
Atsuya Suzuki, Chihiro Matsui, Ken Takeuchi
2018 J jnl
Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test.
IEICE Trans. Electron.
Yusuke Yamaga, Chihiro Matsui, Yukiya Sakaki, Ken Takeuchi
2017 — conf
22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash.
ESSDERC
Chihiro Matsui, Ken Takeuchi
2017 J jnl
Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory.
Proc. IEEE
Chihiro Matsui, Chao Sun, Ken Takeuchi
2017 J jnl
Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs.
IEICE Trans. Electron.
Tomoaki Yamada, Chihiro Matsui, Ken Takeuchi
2017 J jnl
Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD.
IEEE Trans. Very Large Scale Integr. Syst.
Chihiro Matsui, Asuka Arakawa, Chao Sun, Ken Takeuchi
2016 J jnl
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives.
IEEE Trans. Very Large Scale Integr. Syst.
Chao Sun, Ayumi Soga, Chihiro Matsui, Asuka Arakawa, Ken Takeuchi