Chih-Wei Yao

17 papers B 1C 3Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2022 — conf
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW.
ISSCC
Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho
2022 — conf
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.
ESSCIRC
Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee
2021 — conf
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.
ISSCC
Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho
2021 J jnl
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO.
IEEE J. Solid State Circuits
Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho
2019 J jnl
A 28-nm 75-fs
IEEE J. Solid State Circuits
Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho
2019 J jnl
A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits
Jongwoo Lee, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ilyong Jong, Sanghyun Baek, Jae Hoon Lee, Ronghua Ni, Yongrong Zuo, Chih-Wei Yao, Seungchan Heo, Sangwook Han, Thomas Byunghak Cho, Inyup Kang, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Ji-Soo Chang, Sanghoon Kang
2019 — conf
A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS.
ISSCC
Jongwoo Lee, Sangwook Han, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Su-Seob Ahn, Sanghoon Kang, Quang-Diep Bui, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ronghua Ni, Yongrong Zuo, Ilyong Jong, Chih-Wei Yao, Seungchan Heo, Thomas Byunghak Cho, Inyup Kang
2017 — conf
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.
ISSCC
Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho
2017 J jnl
A 14-nm 0.14-ps
IEEE J. Solid State Circuits
Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho
2013 J jnl
A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO.
IEEE J. Solid State Circuits
Chih-Wei Yao, Alan N. Willson Jr.
2009 J jnl
A Programmable 25-MHz to 6-GHz K
IEEE Trans. Circuits Syst. I Regul. Pap.
Jae Y. Kim, Chih-Wei Yao, Alan N. Willson Jr.
2009 C conf
Frequency Synthesis with Arbitrary Input Clock Rate and Rational K/L Multiplier Ratio.
ISCAS
Chih-Wei Yao, Alan N. Willson Jr.
2008 C conf
A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation.
ISCAS
Jae Y. Kim, Chih-Wei Yao, Alan N. Willson Jr.
2006 — conf
A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion.
ISSCC
Chih-Wei Yao, Alan N. Willson Jr.
2006 C conf
Energy circulation quadrature LC-VCO.
ISCAS
Chih-Wei Yao, Alan N. Willson Jr.
2004 — conf
A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial data.
CICC
Chih-Wei Yao, Hiep T. Pham, Alan N. Willson Jr.
1996 B conf
Pattern classification approach to characterizing solitary pulmonary nodules imaged on high-resolution computed tomography.
Image Processing
Michael F. McNitt-Gray, Eric M. Hart, Jonathan G. Goldin, Chih-Wei Yao, Denise R. Aberle