Chih-Wei Liu - RankMe

73 papers A 1C 16Misc 2Journal 26Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 40-nm 209-TOPS/W Reinforcement Learning Processor With Full Speculation Exploitation and Inference-Training Parallel Processing. IEEE J. Solid State Circuits Shih-Hao Chen, Ping-Sheng Wu, Brian Dean Soon, Chao-Hung Chen, Chih-Wei Liu, Chun-Lung Hsu, Chia-Hsiang Yang
2025	—	`conf`	A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing. CICC Shih-Hao Chen, Ping-Sheng Wu, Brian Dean Soon, Chao-Hung Chen, Chun-Lung Hsu, Chih-Wei Liu, Chia-Hsiang Yang
2025	J	`jnl`	Score-based matching for city-scale multi-target multi-camera vehicle tracking. Multim. Tools Appl. Zong-Ye Yang, Chih-Wei Liu, Chao-Hung Chen, Chao-Wei Chen, Ming-Chun Hsyu
2024	J	`jnl`	A Regional Efficiency Assessment of Long-Term Care Services in Taiwan. Syst. Ming-Chung Chang, Jin-Li Hu, Chih-Wei Liu
2024	C	`conf`	Motion Controller Design with Automatic Loop Shaping and Minimum Tracking Errors. ACC Tesheng Hsiao, Chih-Wei Liu
2022	J	`jnl`	Voltage Control of IPMSM Servo Drive in Constant Power Region With Intelligent Parameter Estimation. IEEE Access Faa-Jeng Lin, Chih-Wei Liu, Po-Lun Wang
2021	J	`jnl`	Area Efficient High-Performance Digitally Controlled Power Management Unit. IEEE Trans. Ind. Electron. Chih-Wei Liu, Le-Ren Chang-Chien
2021	—	`conf`	CSAnet: High Speed Channel Spatial Attention Network for Mobile ISP. CVPR Workshops Ming-Chun Hsyu, Chih-Wei Liu, Chao-Hung Chen, Chao-Wei Chen, Wen-Chia Tsai
2021	J	`jnl`	Phase sequence interchange scheme for suppressing transient cross regulation on the compensator controlled and non-compensator controlled single-inductor dual-output buck converter. IET Circuits Devices Syst. Chun-Hsun Wu, Bu-Wei Chen, Wei-Hung Ko, Chih-Wei Liu, Le-Ren Chang-Chien
2020	C	`conf`	A Low Latency NN-Based Cyclic Jacobi EVD Processor for DOA Estimation in Radar System. ISCAS Chih-Wei Liu, Jia-Yu Wu, Kang-Chun Huang
2020	J	`jnl`	Auto-tuning charge balance control for improving transient response on buck converter. Int. J. Circuit Theory Appl. Chih-Wei Liu, Hung-Yu Chen, Le-Ren Chang-Chien
2020	—	`conf`	Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor. VLSI-DAT Hong-Ke Lin, Pin-Han Lin, Chih-Wei Liu
2020	C	`conf`	Pipeline Signal Process Scheme for Saving Power Module Controllers in Power Management Unit. ISCAS Chih-Wei Liu, Le-Ren Chang-Chien
2019	—	`conf`	Energy Efficient CNN Inference Accelerator Using Fast Fourier Transform. VLSI-DAT Ya-Chin Chung, Po-Hsiang Cheng, Chih-Wei Liu
2019	J	`jnl`	FFT-Based Multirate Signal Processing for 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank. IEEE Trans. Circuits Syst. II Express Briefs Chih-Wei Liu, Chia-Kai Chan, Po-Hsiang Cheng, Hsin-Yuan Lin
2019	—	`conf`	High-Throughput 64K-point FFT Processor for THz Imaging Radar System. VLSI-DAT Chia-Kai Chan, Hong-Ke Lin, Chih-Wei Liu
2018	J	`jnl`	Effects of banner Ad shape and the schema creating process on consumer internet browsing behavior. Comput. Hum. Behav. Chih-Wei Liu, Shao-Kang Lo, Ai-Yun Hsieh, Yujong Hwang
2017	J	`jnl`	What consumers see when time is running out: Consumers' browsing behaviors on online shopping websites when under time pressure. Comput. Hum. Behav. Chih-Wei Liu, Ai-Yun Hsieh, Shao-Kang Lo, Yujong Hwang
2016	J	`jnl`	A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor. IEEE Trans. Computers Chih-Wei Liu, Shih-Hao Ou, Kuo-Chiang Chang, Tsung-Ching Lin, Shin-Kai Chen
2016	J	`jnl`	A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems. IEEE ACM Trans. Audio Speech Lang. Process. Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
2016	—	`conf`	Binaural-cue-based noise reduction using multirate quasi-ANSI filter bank for hearing aids. APCCAS Huei-Shiuan Tang, Cheng-Yen Yang, Chih-Wei Liu, Chia-Cheng Chien
2016	—	`conf`	DeAr: A framework for power-efficient and flexible embedded digital signal processor design. APCCAS Chi-Ming Lee, Yong-Jyun Huang, Chih-Wei Liu, Yarsun Hsu
2015	J	`jnl`	An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids. Integr. Shih-Hao Ou, Kuo-Chiang Chang, Chih-Wei Liu
2014	Misc	`conf`	An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids. ICASSP Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
2014	C	`conf`	An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
2014	C	`conf`	Autonomous tuning method for realizing optimal adaptive voltage positioning scheme. ISCAS Chih-Wei Liu, Le-Ren Chang-Chien
2014	—	`conf`	Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. VLSI-DAT Kuo-Chiang Chang, Ching-Hao Lin, Chih-Wei Liu
2014	—	`conf`	Optimized memory access support for data layout conversion on heterogeneous multi-core systems. ESTIMedia Chia-Chen Hsu, Cheng-Yen Lin, Shin-Kai Chen, Chih-Wei Liu, Jenq Kuen Lee
2014	J	`jnl`	Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture. Int. J. Parallel Program. Shin-Kai Chen, Cheng-Yu Hung, Ching-Chih Chen, Chih-Wei Liu
2014	J	`jnl`	Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu
2013	J	`jnl`	10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. Chih-Wei Liu, Kuo-Chiang Chang, Ming-Hsun Chuang, Ching-Hao Lin
2013	—	`conf`	A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications. VLSI-DAT Tsung-Ching Lin, Shin-Kai Chen, Chih-Wei Liu
2013	C	`conf`	A successful application of big data storage techniques implemented to criminal investigation for telecom. APNOMS Ju-Chi Tseng, Hsin-Cheng Tseng, Chih-Wei Liu, Chia Chun Shih, Kuo-Yu Tseng, Cheng-Yu Chou, Chia-Hsuan Yu, Fang-Sun Lu
2013	J	`jnl`	Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). IEEE Trans. Circuits Syst. I Regul. Pap. Shin-Kai Chen, Chih-Wei Liu, Tsung-Yi Wu, An-Chi Tsai
2013	—	`conf`	Spatial-cue-based multi-band binaural noise reduction for hearing aids. SiPS Cheng-Yen Yang, Wen-Sheng Chou, Kuo-Chiang Chang, Chih-Wei Liu, Tai-Shih Chi, Shyh-Jye Jou
2012	C	`conf`	A low power hearing aid computing platform using lightweight processing elements. ISCAS Kuo-Chiang Chang, Yu-Wen Chen, Yu-Ting Kuo, Chih-Wei Liu
2012	C	`conf`	A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. ISCAS Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, Chih-Wei Liu
2012	C	`conf`	Challenges of system virtualization. APNOMS Cheng-Yu Chou, Chih-Wei Liu, Kuo-Yu Tseng, Chien-Wei Cheng, Fang-Sun Lu
2012	—	`conf`	Complexity-effective auditory compensation with a controllable filter for digital hearing aids. ASP-DAC Ya-Ting Chang, Kuo-Chiang Chang, Yu-Ting Kuo, Chih-Wei Liu
2012	—	`conf`	Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids. VLSI-DAT Ching-Hao Lin, Kuo-Chiang Chang, Ming-Hsun Chuang, Chih-Wei Liu
2012	—	`conf`	Early Stage Codesign of Multi-PE SIMD Engine: A Case Study on Object Detection. ICPP Workshops Shin-Kai Chen, Sheng-Yun Wu, Yu-Kai Yen, Chih-Wei Liu
2011	J	`jnl`	Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. EURASIP J. Adv. Signal Process. Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
2010	—	`conf`	Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu
2010	C	`conf`	Complexity-effective dynamic range compression for digital hearing aids. ISCAS Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
2010	J	`jnl`	Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chih-Wei Liu
2010	C	`conf`	Improving energy efficiency of functional units by exploiting their data-dependent latency. ISCAS Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu
2010	—	`conf`	Support of Android lab modules for embedded system curriculum. WESE Meng-Ting Wang, Po-Chun Huang, Jenq Kuen Lee, Shang-Hong Lai, Jyh-Shing Roger Jang, Chun-Fa Chang, Chih-Wei Liu, Tei-Wei Kuo, Steve Liao
2009	—	`conf`	Parallel object detection on multicore platforms. SiPS Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu
2009	—	`conf`	Ultra low-power ANSI S1.11 filter bank for digital hearing aids. ASP-DAC Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu
2008	C	`conf`	Complexity-effective auditory compensation for digital hearing aids. ISCAS Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, Shuenn-Tsong Young
2008	J	`jnl`	Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. J. Signal Process. Syst. Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao
2008	C	`conf`	Improving datapathutilization of programmable DSP with composite functional units. ISCAS Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu
2008	—	`conf`	Multithreaded coprocessor interface for multi-core multimedia SoC. ASP-DAC Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu
2007	J	`jnl`	A View of Gaussian Elimination Applied to Early Stopped Berklekamp-Massey Algorithm. IEEE Trans. Commun. Chih-Wei Liu, Chung-Chin Lu
2007	J	`jnl`	A View of Gaussian Elimination Applied to Early-Stopped Berlekamp-Massey Algorithm. IEEE Trans. Commun. Chih-Wei Liu, Chung-Chin Lu
2007	—	`conf`	Design of ANSI S1.11 Filter Bank for Digital Hearing Aids. ICECS Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Wei-Han Chang, Chih-Wei Liu, Shuenn-Tsong Young
2007	C	`conf`	Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
2007	C	`conf`	Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ISCAS Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu
2007	J	`jnl`	Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu
2007	—	`conf`	Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ASP-DAC Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu
2006	—	`conf`	A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
2006	J	`jnl`	A Compact DSP Core with Static Floating-Point Arithmetic. J. VLSI Signal Process. Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen
2006	—	`conf`	Carry Estimation for Two's Complement Fixed-Width Multipliers. SiPS Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu
2006	Misc	`conf`	KIDBSCAN: A New Efficient Data Clustering Algorithm. ICAISC Cheng-Fa Tsai, Chih-Wei Liu
2006	C	`conf`	Programmable FIR filter with adder-based computing engine. ISCAS Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
2005	—	`conf`	A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
2005	A	`conf`	Architecture for area-efficient 2-D transform in H.264/AVC. ICME Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
2005	—	`conf`	Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen
2005	—	`conf`	Pipelining technique for energy-aware datapaths. ISCAS (2) Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
2004	—	`conf`	A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
2004	—	`conf`	Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
2000	J	`jnl`	Loss behavior in space priority queue with batch Markovian arrival process - discrete-time case. Perform. Evaluation Yung-Chung Wang, Chih-Wei Liu, Chung-Chin Lu
1999	J	`jnl`	A Systolic Array Implementation of the Feng-Rao Algorithm. IEEE Trans. Computers Chih-Wei Liu, Kuo-Tai Huang, Chung-Chin Lu