| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2023 | J | jnl |
IEEE J. Emerg. Sel. Topics Circuits Syst.
|
| 2022 | C | conf |
ISCAS
|
| 2022 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2022 | C | conf |
ISCAS
|
| 2021 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2020 | — | conf |
A-SSCC
|
| 2020 | C | conf |
ISCAS
|
| 2019 | — | conf |
A-SSCC
|
| 2018 | C | conf |
ISCAS
|
| 2017 | J | jnl |
IEEE J. Emerg. Sel. Topics Circuits Syst.
|
| 2017 | — | conf |
ASICON
|
| 2017 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2017 | C | conf |
ISCAS
|
| 2016 | C | conf |
ISCAS
|
| 2016 | J | jnl |
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2016 | — | conf |
APCCAS
|
| 2015 | — | conf |
ICCE-TW
|
| 2014 | J | jnl |
EURASIP J. Adv. Signal Process.
|
| 2014 | J | jnl |
Wirel. Pers. Commun.
|
| 2012 | — | conf |
ISPACS
|
| 2009 | J | jnl |
Neural Comput. Appl.
|
| 2008 | J | jnl |
IEICE Trans. Commun.
|
| 2007 | J | jnl |
Wirel. Pers. Commun.
|
| 2007 | J | jnl |
IEICE Trans. Commun.
|
| 2006 | J | jnl |
J. VLSI Signal Process.
|