Chih-Tsun Huang

79 papers A* 5A 8B 1C 3Misc 4Journal 12Unranked 46

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Low-Complexity and Reconfigurable Design for Nonlinear Function Approximation in Transformers. IEEE Trans. Circuits Syst. II Express Briefs Qi-Xian Wu, Shu-Sian Teng, Ming-Der Shieh, Chih-Tsun Huang, Juin-Ming Lu
2025	C	`conf`	A Low-complexity and Reconfigurable Design for Nonlinear Function Approximation in Transformers. ISCAS Qi-Xian Wu, Shu-Sian Teng, Ming-Der Shieh, Chih-Tsun Huang, Juin-Ming Lu
2025	—	`conf`	An Adaptive Scheme of Threshold Adjustment for Dynamic Sparsity Extraction of Self-Attention Network. AICAS Yong-Lun Xiao, Chia-Wei Chang, Cheng-Ting Shih, Jing-Jia Liou, Chih-Tsun Huang, Yao-Hua Chen, Juin-Ming Lu
2025	—	`conf`	Fault Injection and Tolerance Analysis of Battery Management Systems Using SystemC-AMS. ITC-Asia Hao-Yang Chi, Chih-Tsun Huang, Jing-Jia Liou, Harry H. Chen
2025	—	`conf`	HEADS: Head-Wise Efficient and Adaptive Sparsification for Transformer-Based Models. AICAS Yu-Sung Lee, Jyun-Siou Huang, Yao-Hua Chen, Chih-Tsun Huang
2025	A	`conf`	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks. ITC Po-Sheng Chiu, Chih-Yu Hsu, Chih-Tsun Huang, Jing-Jia Liou
2024	—	`conf`	BEACON: Block-wise Efficient Architecture Co-optimization for DNN-HW-Mapping with Zero-cost Evaluation and Progressive Distillation. SOCC Jiun-Kai Yang, Yao-Hua Chen, Chih-Tsun Huang
2024	—	`conf`	Towards Efficient Visual Attention Prediction for 360 Degree Videos. AIxVR Herman Prawiro, Tse-Yu Pan, Chun-Kai Yang, Chih-Tsun Huang, Min-Chun Hu
2023	—	`conf`	Efficient Hand Gesture Recognition using Multi-Task Multi-Modal Learning and Self-Distillation. MMAsia Jie-Ying Li, Herman Prawiro, Chia-Chen Chiang, Hsin-Yu Chang, Tse-Yu Pan, Chih-Tsun Huang, Min-Chun Hu
2023	—	`conf`	HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. SOCC Jyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou
2023	C	`conf`	MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. ICCD Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu
2023	—	`conf`	Optimization of AI SoC with Compiler-assisted Virtual Design Platform. ISPD Chih-Tsun Huang, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung, Shih-Chieh Chang
2022	—	`conf`	Efficient Segment-wise Pruning for DCNN Inference Accelerators. VLSI-DAT Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu
2022	—	`conf`	Fast DNN-based Mechatronics Prototyping Platform on Robotic Arm Control. AICAS Yu-Chien Chung, Hao-Hsiang Lian, Yong-Lun Xiao, Chih-Tsun Huang, Jing-Jia Liou
2021	—	`conf`	Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator. SoCC Che-Hao Chang, Chih-Tsun Huang
2021	—	`conf`	Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks. AICAS Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-yu Chen, Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu
2019	A	`conf`	Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators. DATE Hao-Ning Wu, Chih-Tsun Huang
2019	—	`conf`	Efficient Dynamic Fixed-Point Quantization of CNN Inference Accelerators for Edge Devices. VLSI-DAT Yueh-Chi Wu, Chih-Tsun Huang
2017	—	`conf`	Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. VLSI-DAT Ting-Shuo Hsu, Chao-Chieh Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu
2017	—	`conf`	Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu
2016	B	`conf`	IoT: Source of test challenges. ETS Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes
2015	—	`conf`	Application-level embedded communication tracer for many-core systems. ASP-DAC Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien
2015	—	`conf`	Design of a scalable many-core processor for embedded applications. ASP-DAC Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou
2014	—	`conf`	Design of low-cost elliptic curve cryptographic engines for ubiquitous security. VLSI-DAT Hsin-Yu Ting, Chih-Tsun Huang
2014	—	`conf`	Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu
2013	J	`jnl`	AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
2013	—	`conf`	Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. MES Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou
2012	—	`conf`	Design and analysis of a many-core processor architecture for multimedia applications. APSIPA Jyu-Yuan Lai, Po-Yu Chen, Ting-Shuo Hsu, Chih-Tsun Huang, Jing-Jia Liou
2011	A*	`conf`	A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
2011	J	`jnl`	Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications. IEEE Trans. Very Large Scale Integr. Syst. Jyu-Yuan Lai, Chih-Tsun Huang
2011	—	`conf`	Hardware/software co-designed accelerator for vector graphics applications. SASP Shuo-Hung Chen, Hsiao-Mei Lin, Hsin-Wen Wei, Yi-Cheng Chen, Chih-Tsun Huang, Yeh-Ching Chung
2011	A*	`conf`	Reliability analysis and improvement for multi-level non-volatile memories with soft information. DAC Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, Chih-Tsun Huang
2011	—	`conf`	TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. ASP-DAC Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung
2010	—	`conf`	AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
2010	C	`conf`	High-performance architecture for Elliptic Curve Cryptography over binary field. ISCAS Jyu-Yuan Lai, Tzu-Yu Hung, Kai-Hsiang Yang, Chih-Tsun Huang
2010	J	`jnl`	Single- and Multi-core Configurable AES Architectures for Flexible Security. IEEE Trans. Very Large Scale Integr. Syst. Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu, Chih-Tsun Huang
2009	J	`jnl`	A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography. IEEE Trans. Circuits Syst. II Express Briefs Jyu-Yuan Lai, Chih-Tsun Huang
2008	A*	`conf`	An embedded infrastructure of debug and trace interface for the DSP platform. DAC Ming-Chang Hsieh, Chih-Tsun Huang
2008	—	`conf`	Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. ATS Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
2008	J	`jnl`	Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography. IEEE Trans. Very Large Scale Integr. Syst. Jyu-Yuan Lai, Chih-Tsun Huang
2007	—	`conf`	A High-Throughput Low-Power AES Cipher for Network Applications. ASP-DAC Shin-Yi Lin, Chih-Tsun Huang
2007	—	`conf`	A prototype of a wireless-based test system. SoCC Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang
2007	J	`jnl`	BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. IET Comput. Digit. Tech. Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang
2007	J	`jnl`	Optimization of Pattern Matching Circuits for Regular Expression on FPGA. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
2006	A*	`conf`	A network security processor design based on an integrated SOC design and test platform. DAC Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
2006	—	`conf`	Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
2005	Misc	`conf`	A BIST Scheme for FPGA Interconnect Delay Faults. VTS Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
2005	—	`conf`	A configurable AES processor for enhanced security. ASP-DAC Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
2005	—	`conf`	A systematic approach to reducing semiconductor memory test time in mass production. MTDT Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen
2005	—	`conf`	Design and test of a scalable security processor. ASP-DAC Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2004	—	`conf`	An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
2004	—	`conf`	An HMAC processor with integrated SHA-1 and MD5 algorithms. ASP-DAC Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
2004	A	`conf`	An SOC Test Integration Platform and Its Industrial Realization. ITC Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
2004	—	`conf`	Failure Factor Based Yield Enhancement for SRAM Designs. DFT Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu
2004	—	`conf`	On Test and Diagnostics of Flash Memories. Asian Test Symposium Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu
2003	J	`jnl`	A high-throughput low-cost AES processor. IEEE Commun. Mag. Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
2003	—	`conf`	A highly efficient AES cipher chip. ASP-DAC Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
2003	J	`jnl`	Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
2003	—	`conf`	Design of a scalable RSA and ECC crypto-processor. ASP-DAC Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
2003	A	`conf`	FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2003	A	`conf`	Fault Pattern Oriented Defect Diagnosis for Memories. ITC Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
2003	Misc	`conf`	Test and Diagnosis of Word-Oriented Multiport Memories. VTS Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2002	A	`conf`	Diagonal Test and Diagnostic Schemes for Flash Memorie. ITC Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2002	J	`jnl`	Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
2002	—	`conf`	Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2002	Misc	`conf`	RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
2002	—	`conf`	Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2002	—	`conf`	Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2001	—	`conf`	A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
2001	—	`conf`	Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2001	A	`conf`	March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2001	A*	`conf`	Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
2000	—	`conf`	A programmable built-in self-test core for embedded memories. ASP-DAC Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
2000	—	`conf`	BRAINS: A BIST Compiler for Embedded Memories. DFT Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai
2000	A	`conf`	Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
2000	Misc	`conf`	Simulation-Based Test Algorithm Generation for Random Access Memories. VTS Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
1999	J	`jnl`	A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
1999	—	`conf`	RAMSES: A Fast Memory Fault Simulator. DFT Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
1997	—	`conf`	High-speed C-testable systolic array design for Galois-field inversion. ED&TC Chih-Tsun Huang, Cheng-Wen Wu