Chih-Ting Yeh

14 papers C 1Misc 1Journal 4Unranked 8

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Multi-behavior Recommendation with Action Pattern-aware Networks. WI/IAT Chia-Ying Tsao, Chih-Ting Yeh, Jyh-Shing Roger Jang, Yung-Yaw Chen, Chuan-Ju Wang
2021	—	`conf`	A Learning Framework with Disposable Auxiliary Networks for Early Prediction of Product Success. WI/IAT Chih-Ting Yeh, Zhe-Li Lin, Sheng-Chieh Lin, Jing-Kai Lou, Ming-Feng Tsai, Chuan-Ju Wang
2021	—	`conf`	An Exploration Study of Multi-stage Conversational Passage Retrieval: Paraphrase Query Expansion and Multi-view Point-wise Ranking. TREC Jia-Huei Ju, Chih-Ting Yeh, Cheng-Wei Lin, Chia-Ying Tsao, Jun-En Ding, Chuan-Ju Wang, Ming-Feng Tsai
2019	Misc	`conf`	Speaker Characterization Using TDNN-LSTM Based Speaker Embedding. ICASSP Chia-Ping Chen, Su-Yu Zhang, Chih-Ting Yeh, Jia-Ching Wang, Tenghui Wang, Chien-Lin Huang
2019	—	`conf`	以三元組損失微調時延神經網路語者嵌入函數之語者辨識系統(Time Delay Neural Network-based Speaker Embedding Function Fine-tuned with Triplet Loss for Distance-based Speaker Recognition). ROCLING Chih-Ting Yeh, Po-Chin Wang, Su-Yu Zhang, Chia-Ping Chen, Shan-Wen Hsiao, Bo-Cheng Chan, Chung-Li Lu
2018	—	`conf`	結合卷積神經網路與遞迴神經網路於推文極性分類 (Combining Convolutional Neural Network and Recurrent Neural Network for Tweet Polarity Classification) [In Chinese]. ROCLING Chih-Ting Yeh, Chia-Ping Chen
2013	—	`conf`	Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. VLSI-DAT Chih-Ting Yeh, Ming-Dou Ker
2013	J	`jnl`	PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. Microelectron. Reliab. Chih-Ting Yeh, Ming-Dou Ker
2012	J	`jnl`	New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Chih-Ting Yeh, Ming-Dou Ker
2012	—	`conf`	New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. VLSI-DAT Chih-Ting Yeh, Ming-Dou Ker
2012	J	`jnl`	Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications. Microelectron. Reliab. Chih-Ting Yeh, Ming-Dou Ker
2011	C	`conf`	Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. ISCAS Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker
2010	J	`jnl`	Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. IEEE J. Solid State Circuits Chih-Ting Yeh, Ming-Dou Ker
2008	—	`conf`	Active ESD protection design against cross-power-domain ESD stresses in CMOS integrated circuits. APCCAS Shih-Hung Chen, Chih-Ting Yeh