Chih-Sheng Hou

15 papers A 1B 1Misc 3Journal 6Unranked 4
YearRankTypeTitle / Venue / Authors
2016 A conf
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.
ITC
Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2015 J jnl
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Chih-Sheng Hou, Jin-Fu Li
2014 J jnl
A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Sheng Hou, Jin-Fu Li, Ting-Jun Fu
2014 — conf
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.
ATS
Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo
2014 J jnl
Testing Disturbance Faults in Various NAND Flash Memories.
J. Electron. Test.
Chih-Sheng Hou, Jin-Fu Li
2013 Misc conf
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.
VTS
Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013 Misc conf
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs.
VTS
Chih-Sheng Hou, Jin-Fu Li
2013 — conf
An FPGA-based test platform for analyzing data retention time distribution of DRAMs.
VLSI-DAT
Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013 — conf
Testing Disturbance Faults in Various NAND Flash Memories.
Asian Test Symposium
Chih-Sheng Hou, Jin-Fu Li
2012 B conf
Disturbance fault testing on various NAND flash memories.
ETS
Chih-Sheng Hou, Jin-Fu Li
2011 J jnl
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng
2010 J jnl
A Built-in Method to Repair SoC RAMs in Parallel.
IEEE Des. Test Comput.
Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou
2010 Misc conf
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.
VTS
Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li
2010 J jnl
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou
2010 — conf
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs.
DELTA
Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou