Chih-Lung Chen

28 papers C 4Journal 17Unranked 7
YearRankTypeTitle / Venue / Authors
2022 J jnl
CoNN-IDS: Intrusion detection system based on collaborative neural networks and agile training.
Comput. Secur.
Jung-San Lee, Ying-Chin Chen, Chit-Jie Chew, Chih-Lung Chen, Thu-Nguyet Huynh, Chung-Wei Kuo
2021 J jnl
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Yong-Ru Lu, Shen-Iuan Liu, Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, Ying-Hsi Lin
2021 J jnl
Preserving indomitable DDoS vitality through resurrection social hybrid botnet.
Comput. Secur.
Chit-Jie Chew, Ying-Chin Chen, Jung-San Lee, Chih-Lung Chen, Kuo-Yu Tsai
2020 J jnl
Towards Accurate and Efficient Classification of Power System Contingencies and Cyber-Attacks Using Recurrent Neural Networks.
IEEE Access
Wei-Chih Hong, Ding-Ray Huang, Chih-Lung Chen, Jung-San Lee
2016 J jnl
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang
2016 — conf
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.
A-SSCC
Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2016 J jnl
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 — conf
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.
ESSCIRC
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 C conf
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.
ISCAS
Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.
A-SSCC
Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
A 7.11mJ/Gb/query data-driven machine learning processor (D
VLSIC
Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee
2014 C conf
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.
ISCAS
Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2013 — conf
Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes.
WCSP
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
2013 J jnl
An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes.
IEEE Commun. Lett.
Hsiu-Chi Chang, Chih-Lung Chen, Hsie-Chia Chang
2013 J jnl
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection.
IEEE Trans. Multim.
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, John K. Zao, Hsie-Chia Chang
2013 J jnl
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes.
IEEE Commun. Lett.
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
2012 J jnl
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.
IEEE J. Solid State Circuits
Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee
2012 J jnl
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits
Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2012 C conf
An improved LT encoding scheme with extended chain lengths.
ISITA
Kuo-Kuang Yen, Chih-Lung Chen, Hsie-Chia Chang
2012 — conf
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes.
APCCAS
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
2012 C conf
Stochastic decoding for LDPC convolutional codes.
ISCAS
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2010 J jnl
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.
IEEE J. Solid State Circuits
Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2009 — conf
A 11.5-Gbps LDPC decoder based on CP-PEG code construction.
ESSCIRC
Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee
2009 J jnl
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 J jnl
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.
IEEE J. Solid State Circuits
Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou