Chih-Kong Ken Yang

95 papers A* 2A 1C 5Journal 56Unranked 31

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. IEEE Trans. Very Large Scale Integr. Syst. Zhichao Chen, Ali H. Hassan, Rhesa Muhammad Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta
2024	—	`conf`	A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB. BCICTS Christopher Chen, Yan Zhang, Hao-Yu Chien, Jiazhang Song, Jia Zhou, Chao-Jen Tien, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang
2024	—	`conf`	Cryogenic Alternative: CMOS Versus Dynamic-Based Logic. MWSCAS Ali H. Hassan, Puneet Gupta, Sudhakar Pamarti, Chih-Kong Ken Yang
2024	—	`conf`	Invited Paper: A Pseudo-Differential Architecture for Low-Power Voltage-to-Time Converters. MWSCAS Ali H. Hassan, Hassan Mostafa, Chih-Kong Ken Yang
2022	C	`conf`	A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input. ISCAS Jiazhang Song, Li-Yang Chen, Mau-Chung Frank Chang, Sudhakar Pamarti, Chih-Kong Ken Yang
2022	J	`jnl`	A Pulsed-Coherent Lidar With Sub-10 μm Precision. IEEE J. Solid State Circuits Li-Yang Chen, Abhinav Kumar Vinod, James F. McMillan, Hangbo Yang, Chee Wei Wong, Chih-Kong Ken Yang
2022	J	`jnl`	A Scalable 20V Charge-Pump-Based Driver in 65nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Mostafa Toubar, Yousr Ismail, Sameh Ibrahim, Chih-Kong Ken Yang
2021	C	`conf`	A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. ISCAS Liangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen
2021	—	`conf`	A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA. CICC Li-Yang Chen, Abhinav Kumar Vinod, James F. McMillan, Chee Wei Wong, Chih-Kong Ken Yang
2021	—	`conf`	A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS. ESSCIRC Yan Zhang, Chia-Jen Liang, Christopher Chen, Andrew Liu, Jason Woo, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang
2020	J	`jnl`	A 92%-Efficiency Battery Powered Hybrid DC-DC Converter for IoT Applications. IEEE Trans. Circuits Syst. Mahmoud R. Elhebeary, Chih-Kong Ken Yang
2020	J	`jnl`	A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot. IEEE Trans. Circuits Syst. Mahmoud R. Elhebeary, Chih-Kong Ken Yang
2019	—	`conf`	A 19-GHz Pulsed-Coherent ToF Receiver With 40-μm Precision for Laser Ranging Systems. ESSCIRC Li-Yang Chen, Chih-Kong Ken Yang
2019	—	`conf`	An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications. ESSCIRC Mahmoud R. Elhebeary, Li-Yang Chen, Sudhakar Pamarti, Chih-Kong Ken Yang
2019	—	`conf`	An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications. MWSCAS Mahmoud R. Elhebeary, Chih-Kong Ken Yang
2017	J	`jnl`	A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology. IEEE J. Solid State Circuits Yousr Ismail, Haechang Lee, Sudhakar Pamarti, Chih-Kong Ken Yang
2015	J	`jnl`	A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology. IEEE J. Solid State Circuits Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
2015	J	`jnl`	A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology. IEEE J. Solid State Circuits Ming-Shuan Chen, Chih-Kong Ken Yang
2015	J	`jnl`	A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters. IEEE Trans. Very Large Scale Integr. Syst. Jintae Kim, Siamak Modjtahedi, Chih-Kong Ken Yang
2015	—	`conf`	A low-PDP and low-area repeater using passive CTLE for on-chip interconnects. VLSIC Ming-Shuan Chen, Mau-Chung Frank Chang, Chih-Kong Ken Yang
2015	C	`conf`	Effects of Active Cooling on Workload Management in High Performance Processors. CLOSER Won Ho Park, Chih-Kong Ken Yang
2014	—	`conf`	23.8 A 34V charge pump in 65nm bulk CMOS technology. ISSCC Yousr Ismail, Haechang Lee, Sudhakar Pamarti, Chih-Kong Ken Yang
2014	—	`conf`	A 12-V charge pump-based square wave driver in 65-nm CMOS technology. A-SSCC Yousr Ismail, Chih-Kong Ken Yang
2014	—	`conf`	A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS. CICC Ming-Shuan Chen, Chih-Kong Ken Yang
2014	C	`conf`	A compact stacked-device output driver in low-voltage CMOS Technology. ISCAS Yousr Ismail, Chih-Kong Ken Yang
2014	J	`jnl`	Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters. IEEE Trans. Very Large Scale Integr. Syst. Jintae Kim, Siamak Modjtahedi, Chih-Kong Ken Yang
2014	J	`jnl`	Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression. IEEE Trans. Very Large Scale Integr. Syst. Henry Park, Chih-Kong Ken Yang
2013	J	`jnl`	A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection. IEEE J. Solid State Circuits Ming-Shuan Chen, Amr Amin Hafez, Chih-Kong Ken Yang
2013	J	`jnl`	A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding. IEEE J. Solid State Circuits Tamer A. Ali, Robert J. Drost, Ron Ho, Chih-Kong Ken Yang
2013	—	`conf`	A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. ISSCC Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
2013	—	`conf`	A bipolar >40-V driver in 45-nm SOI CMOS technology. CICC Yousr Ismail, Chang-Jin Kim, Chih-Kong Ken Yang
2013	C	`conf`	A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS. ISCAS Ramy Yousry, Henry Park, E-Hung Chen, Chih-Kong Ken Yang
2013	J	`jnl`	An INL Yield Model of the Digital-to-Analog Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Henry Park, Chih-Kong Ken Yang
2013	J	`jnl`	Analysis and Design of Superharmonic Injection-Locked Multipath Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Amr Amin Hafez, Chih-Kong Ken Yang
2013	J	`jnl`	Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors. IEEE Trans. Very Large Scale Integr. Syst. Won Ho Park, Chih-Kong Ken Yang
2013	J	`jnl`	In Situ SRAM Static Stability Estimation in 65-nm CMOS. IEEE J. Solid State Circuits Henry Park, Chih-Kong Ken Yang
2013	J	`jnl`	Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs. IEEE Trans. Circuits Syst. I Regul. Pap. Fengbo Ren, Henry Park, Chih-Kong Ken Yang, Dejan Markovic
2012	—	`conf`	A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding. VLSIC Tamer A. Ali, Won Ho Park, Preeti Mulage, E-Hung Chen, Ron Ho, Chih-Kong Ken Yang
2012	—	`conf`	A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). ISQED Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic
2012	—	`conf`	A low-power highly multiplexed parallel PRBS generator. CICC Ming-Shuan Chen, Chih-Kong Ken Yang
2012	J	`jnl`	Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter. IEEE Trans. Circuits Syst. II Express Briefs Henry Park, Chih-Kong Ken Yang
2012	J	`jnl`	Power Optimized ADC-Based Serial Link Receiver. IEEE J. Solid State Circuits E-Hung Chen, Ramy Yousry, Chih-Kong Ken Yang
2011	—	`conf`	A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning. ISSCC Tamer A. Ali, Amr Amin Hafez, Robert J. Drost, Ronald Ho, Chih-Kong Ken Yang
2011	—	`conf`	Analysis of STT-RAM cell design with multiple MTJs per access. NANOARCH Henry Park, Richard Dorrance, Amr Amin Hafez, Fengbo Ren, Dejan Markovic, Chih-Kong Ken Yang
2011	J	`jnl`	Design and Optimization of Multipath Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Amr Amin Hafez, Chih-Kong Ken Yang
2011	J	`jnl`	Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. Jaeha Kim, E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang
2011	J	`jnl`	Multilevel Power Optimization of Pipelined A/D Converters. IEEE Trans. Very Large Scale Integr. Syst. Jintae Kim, S. Limotyrakis, Chih-Kong Ken Yang
2011	—	`conf`	Scalability and design-space analysis of a 1T-1MTJ memory cell. NANOARCH Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin Hafez, Chih-Kong Ken Yang, Dejan Markovic
2010	J	`jnl`	A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. IEEE J. Solid State Circuits Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2010	J	`jnl`	ADC-Based Serial I/O Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. E-Hung Chen, Chih-Kong Ken Yang
2010	—	`conf`	Clocking Links in Multi-chip Packages: A Case Study. Hot Interconnects Tamer A. Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon K. Lexau, Chih-Kong Ken Yang, Ron Ho
2010	J	`jnl`	Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jintae Kim, Lieven Vandenberghe, Chih-Kong Ken Yang
2010	J	`jnl`	Guest Editorial for Special Issue on High-Performance Multichip Interconnections. IEEE Trans. Circuits Syst. II Express Briefs Vladimir Stojanovic, Chih-Kong Ken Yang, Ron Ho
2009	J	`jnl`	A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization. IEEE J. Solid State Circuits Aida Varzaghani, Chih-Kong Ken Yang
2009	—	`conf`	A nonlinear phase detector for digital phase locked loops. CICC Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2009	A*	`conf`	A stochastic jitter model for analyzing digital timing-recovery circuits. DAC James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi
2009	—	`conf`	ADC-based serial I/O receivers. CICC Chih-Kong Ken Yang, E-Hung Chen
2009	J	`jnl`	An LC-Based Clock Buffer With Tunable Injection Locking. IEEE J. Solid State Circuits Li-min Lee, Chih-Kong Ken Yang
2009	J	`jnl`	Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages. IEEE J. Solid State Circuits Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2008	J	`jnl`	A Comprehensive Delay Model for CMOS CML Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Utku Seckin, Chih-Kong Ken Yang
2008	J	`jnl`	Edge and Data Adaptive Equalization of Serial-Link Transceivers. IEEE J. Solid State Circuits Jackie Koon Lun Wong, E-Hung Chen, Chih-Kong Ken Yang
2008	—	`conf`	Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage. CICC Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2008	J	`jnl`	Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. IEEE J. Solid State Circuits E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Hae-Chang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang
2007	J	`jnl`	A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. IEEE J. Solid State Circuits Jackie Koon Lun Wong, Alexander V. Rylyakov, Chih-Kong Ken Yang
2007	J	`jnl`	A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. IEEE J. Solid State Circuits Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman
2007	—	`conf`	A Comprehensive Phase-Transfer Model for Delay-Locked Loops. CICC James R. Burnham, Gu-Yeon Wei, Chih-Kong Ken Yang, Haitham A. Hindi
2007	J	`jnl`	A Large-Swing Transformer-Boosted Serial Link Transmitter With > V IEEE J. Solid State Circuits Jintae Kim, Hamid Hatamkhani, Chih-Kong Ken Yang
2007	—	`conf`	An Adaptive Low-Jitter LC-Based Clock Distribution. ISSCC Li-min Lee, Chih-Kong Ken Yang
2007	A	`conf`	Device-circuit co-optimization for mixed-mode circuit design via geometric programming. ICCAD Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang
2007	J	`jnl`	Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. IEEE Trans. Very Large Scale Integr. Syst. Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang
2007	J	`jnl`	Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs Ping-Hsuan Hsieh, Chih-Kong Ken Yang
2006	J	`jnl`	A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter. IEEE J. Solid State Circuits Aida Varzaghani, Chih-Kong Ken Yang
2006	J	`jnl`	A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration. IEEE J. Solid State Circuits Aida Varzaghani, Chih-Kong Ken Yang
2006	—	`conf`	A Serial-Link Transceiver with Transition Equalization. ISSCC Koon-Lun Jackie Wong, Chih-Kong Ken Yang
2006	J	`jnl`	A Study of the Optimal Data Rate for Minimum Power of I/Os. IEEE Trans. Circuits Syst. II Express Briefs Hamid Hatamkhani, Chih-Kong Ken Yang
2006	J	`jnl`	A sub-10-ps multiphase sampling system using redundancy. IEEE J. Solid State Circuits Li-min Lee, Daniel Weinlader, Chih-Kong Ken Yang
2006	—	`conf`	An 8Gb/s Transformer-Boosted Transmitter with >V ISSCC Jintae Kim, Hamid Hatamkhani, Chih-Kong Ken Yang
2006	J	`jnl`	Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Jan Van der Spiegel, Ram K. Krishnamurthy, Sreedhar Natarajan, Chih-Kong Ken Yang
2006	A*	`conf`	Power-centric design of high-speed I/Os. DAC Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang
2004	J	`jnl`	A 27-mW 3.6-gb/s I/O transceiver. IEEE J. Solid State Circuits Jackie Koon Lun Wong, Hamid Hatamkhani, Mozhgan Mansuri, Chih-Kong Ken Yang
2004	J	`jnl`	Offset compensation in comparators with minimum input-referred supply noise. IEEE J. Solid State Circuits Koon-Lun Jackie Wong, Chih-Kong Ken Yang
2003	J	`jnl`	A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation. IEEE J. Solid State Circuits Mozhgan Mansuri, Chih-Kong Ken Yang
2003	—	`conf`	Analysis of timing recovery for multi-Gbps PAM transceivers. CICC Chih-Kong Ken Yang, Koon-Lun Jackie Wong
2003	—	`conf`	CMOS LC oscillator using variable mean frequency. CICC Ping-Hsuan Hsieh, Jack Judy, Chih-Kong Ken Yang
2003	—	`conf`	Evaluation of fully-integrated switching regulators for CMOS process technologies. SoC Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang
2003	J	`jnl`	Methodology for on-chip adaptive jitter minimization in phase-locked loops. IEEE Trans. Circuits Syst. II Express Briefs Mozhgan Mansuri, A. Hadiashar, Chih-Kong Ken Yang
2002	J	`jnl`	Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. IEEE J. Solid State Circuits Mozhgan Mansuri, Dean Liu, Chih-Kong Ken Yang
2002	J	`jnl`	Jitter optimization based on phase-locked loop design parameters. IEEE J. Solid State Circuits Mozhgan Mansuri, Chih-Kong Ken Yang
2001	J	`jnl`	A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS. IEEE J. Solid State Circuits Chih-Kong Ken Yang, Vladimir Stojanovic, Siamak Modjtahedi, Mark A. Horowitz, William F. Ellersick
2000	J	`jnl`	A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. IEEE J. Solid State Circuits Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee
1999	J	`jnl`	A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. IEEE J. Solid State Circuits Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee
1999	J	`jnl`	A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation. IEEE J. Solid State Circuits Katayoun Falakshahi, Chih-Kong Ken Yang, Bruce A. Wooley
1998	J	`jnl`	A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling. IEEE J. Solid State Circuits Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz
1998	J	`jnl`	High-speed electrical signaling: overview and limitations. IEEE Micro Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos
1996	J	`jnl`	A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links. IEEE J. Solid State Circuits Chih-Kong Ken Yang, Mark A. Horowitz