Chih-Da Chien

14 papers A 2C 3Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2016 J jnl
A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications.
IEEE J. Solid State Circuits
Chi-Cheng Ju, Tsu-Ming Liu, Kun-Bin Lee, Yung-Chang Chang, Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng-Jye Hu, Peng-Hao Wang, Yen-Chao Huang, Shun-Hsiang Chuang, Lien-Fei Chen, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen
2015 — conf
18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications.
ISSCC
Chi-Cheng Ju, Tsu-Ming Liu, Kun-Bin Lee, Yung-Chang Chang, Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng-Jye Hu, Peng-Hao Wang, Fu-Chun Yeh, Yen-Chao Huang, Shun-Hsiang Chuang, Lien-Fei Chen, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Ryan Chen, H. Y. Hsu, Kevin Jou
2009 J jnl
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.
ACM Trans. Design Autom. Electr. Syst.
Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
2009 C conf
A Multi-standard Video Decoder for High Definition Video Applications.
ISCAS
Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
2007 — conf
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications.
ISSCC
Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo
2007 A conf
A Low Latency Memory Controller for Video Coding Systems.
ICME
Chih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo
2007 C conf
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation.
ISCAS
Guo-An Jian, Chih-Da Chien, Jiun-In Guo
2006 C conf
A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications.
ISCAS
Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo
2006 J jnl
An Area-Efficient Variable Length Decoder IP Core Design for MPEG-1/2/4 Video Coding Applications.
IEEE Trans. Circuits Syst. Video Technol.
Chih-Da Chien, Keng-Po Lu, Yu-Min Chen, Jiun-In Guo, Yuan-Sun Chu, Ching-Lung Su
2005 — conf
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding.
ISCAS (5)
Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo
2004 A conf
A high-performance MPEG4 bitstream processing core.
ICME
Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo
2004 — conf
A power-aware IP core generator for the one-dimensional discrete Fourier transform.
ISCAS (3)
Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen
2003 — conf
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.
ISCAS (5)
Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin
2002 J jnl
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths.
J. Circuits Syst. Comput.
Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien