Chih-Chi Cheng

25 papers A* 2A 2C 3Journal 8Unranked 10
YearRankTypeTitle / Venue / Authors
2016 A* conf
A patch memory system for image processing and computer vision.
MICRO
Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler
2012 J jnl
Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding.
IEEE J. Solid State Circuits
Rahul Rithe, Chih-Chi Cheng, Anantha P. Chandrakasan
2011 — conf
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications.
ISSCC
Pei-Kuei Tsung, Pin-Chih Lin, Kuan-Yu Chen, Tzu-Der Chuang, Hsin-Jung Yang, Shao-Yi Chien, Li-Fu Ding, Wei-Yin Chen, Chih-Chi Cheng, Tung-Chien Chen, Liang-Gee Chen
2011 — conf
Quad Full-HD transform engine for dual-standard low-power video coding.
A-SSCC
Rahul Rithe, Chih-Chi Cheng, Anantha P. Chandrakasan
2010 — conf
A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine.
CICC
Chih-Chi Cheng, Yi-Min Tsai, Liang-Gee Chen, Anantha P. Chandrakasan
2009 J jnl
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System.
IEEE Trans. Circuits Syst. Video Technol.
Chih-Chi Cheng, Po-Chih Tseng, Liang-Gee Chen
2009 J jnl
iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor.
IEEE J. Solid State Circuits
Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Liang-Gee Chen
2008 A conf
Diastolic arrays: throughput-driven reconfigurable computing.
ICCAD
Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas
2008 J jnl
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Technol.
Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching-Yeh Chen, Shao-Yi Chien, Liang-Gee Chen
2008 — conf
iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor.
ISSCC
Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Chia-Jung Hsu, Liang-Gee Chen
2008 A* conf
iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.
DAC
Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen
2007 J jnl
124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory.
IEEE Trans. Circuits Syst. Video Technol.
Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen
2007 J jnl
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Technol.
Chih-Chi Cheng, Chao-Tsung Huang, Ching-Yeh Chen, Chung-Jr Lian, Liang-Gee Chen
2006 — conf
124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory.
ISSCC
Yu-Wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Chung-Jr Lian, Shao-Yi Chien, Liang-Gee Chen
2006 — conf
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications.
ISSCC
Chia-Ping Lin, Po-Chih Tseng, Yao-Ting Chiu, Siou-Shen Lin, Chih-Chi Cheng, Hung-Chi Fang, Wei-Min Chao, Liang-Gee Chen
2006 C conf
Analysis and VLSI architecture of update step in motion-compensated temporal filtering.
ISCAS
Chih-Chi Cheng, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen
2006 — conf
Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture.
SiPS
Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen
2006 C conf
Frame-level data reuse for motion-compensated temporal filtering.
ISCAS
Ching-Yeh Chen, Yi-Hau Chen, Chih-Chi Cheng, Liang-Gee Chen
2006 — conf
Line Buffer Wordlength Analysis for Line-Based 2-D DWT.
ICASSP (3)
Chih-Chi Cheng, Chao-Tsung Huang, Jing-Ying Chang, Liang-Gee Chen
2006 J jnl
Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling.
IEEE Trans. Signal Process.
Hung-Chi Fang, Yu-Wei Chang, Chih-Chi Cheng, Liang-Gee Chen
2006 J jnl
Precompression Quality-Control Algorithm for JPEG 2000.
IEEE Trans. Image Process.
Yu-Wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Liang-Gee Chen
2006 A conf
Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.
ICME
Yi-Hau Chen, Ching-Yeh Chen, Chih-Chi Cheng, Liang-Gee Chen
2005 C conf
Application Layer Error Correction Scheme for Video Header Protection on Wireless Network.
ISM
Chia-Ho Pan, I-Hsien Lee, Sheng-Chieh Huang, Chih-Chi Cheng, Chung-Jr Lian, Liang-Gee Chen
2005 — conf
Memory efficient JPEG2000 architecture with stripe pipeline scheme.
ICASSP (5)
Hung-Chi Fang, Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Liang-Gee Chen
2005 — conf
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
ISCAS (5)
Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen