Chih-Cheng Hsieh

124 papers C 12Journal 50Unranked 62

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	30.5 A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks. ISSCC Jen-Chun Tien, Win-San Khwa, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Yu-Sheng Kao, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, De-Qi You, Ashwin Sanjay Lele, Brian Crafton, Bo Zhang, Ping-Sheng Wu, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026	J	`jnl`	A 15-bit ROIC With Current-Mode Folding Integration Technique for Microbolometer Thermal Imagers. IEEE Trans. Very Large Scale Integr. Syst. John Carl Joel Salao Marquez, Hsin Yu, Chih-Cheng Hsieh
2026	—	`conf`	A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-in-Memory Macro for Hybrid SNN-CNN Edge Computing. ISSCC Yao-Kai Yeh, Jian-Wei Su, Ting-Hao Hsu, Mai Tseng, Jen-Chun Tien, Ko-Chi Chen, Chih-Yen Yue, Yu-En Lin, Yu-Jia Hu, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Hung-Hsi Hsu, De-Qi You, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026	—	`conf`	A 22nm 96Mb 50.6-to-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN. ISSCC Hung-Hsi Hsu, Win-San Khwa, Yao-Kai Yeh, Chih-Ling Wu, Chang-Yuan Chen, Yen-Che Huang, Yen-hua Lin, Cheng-Feng Chang, Yen-Tung Shao, Jen-Chun Tien, De-Qi You, Ping-Sheng Wu, Bo Zhang, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026	J	`jnl`	A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device. IEEE J. Solid State Circuits Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026	J	`jnl`	A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks. IEEE J. Solid State Circuits De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025	—	`conf`	14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks. ISSCC De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025	—	`conf`	14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices. ISSCC Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2025	J	`jnl`	A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device. IEEE J. Solid State Circuits Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025	J	`jnl`	An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. IEEE J. Solid State Circuits Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	—	`conf`	34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. ISSCC Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	—	`conf`	34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. ISSCC Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024	J	`jnl`	8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	—	`conf`	A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. VLSI Technology and Circuits De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024	J	`jnl`	A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE J. Solid State Circuits Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	—	`conf`	A Low-OSR 5 VLSI Technology and Circuits Pao-Shu Liu, Yu-Hsiang Huang, Chih-Cheng Hsieh
2024	J	`jnl`	A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. IEEE J. Solid State Circuits Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024	—	`conf`	A nMOS-Only Pulse-Width Modulation CMOS Imager with Body Effect Mitigation Using Differential Comparison Technique. A-SSCC Yu-Tang Shen, John Carl Joel Salao Marquez, Chih-Cheng Hsieh
2024	J	`jnl`	An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE J. Solid State Circuits Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	J	`jnl`	An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. IEEE J. Solid State Circuits De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024	J	`jnl`	An algorithm for solving over-determined multivariate quadratic systems over finite fields. Adv. Math. Commun. Lih-Chung Wang, Tzer-Jen Wei, Jian-Ming Shih, Yuh-Hua Hu, Chih-Cheng Hsieh
2023	J	`jnl`	8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. IEEE J. Solid State Circuits Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023	—	`conf`	A -20°C~+107°C 52mk-NETD Reference-cell-free 15-bits ROIC for 80×60 Micro-bolometer Thermal Imager. VLSI Technology and Circuits Hsin Yu, John Carl Joel Salao Marquez, Chih-Cheng Hsieh
2023	J	`jnl`	A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. IEEE J. Solid State Circuits Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh
2023	J	`jnl`	A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive Voltage- Time-Voltage Converter. IEEE J. Solid State Circuits Chih-Cheng Chen, Yu-Hsiang Huang, John Carl Joel Salao Marquez, Chih-Cheng Hsieh
2023	—	`conf`	A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. ISSCC Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2023	—	`conf`	A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. ISSCC Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023	—	`conf`	A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. VLSI Technology and Circuits Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023	J	`jnl`	A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2023	J	`jnl`	A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision. IEEE J. Solid State Circuits Min-Yang Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh
2023	—	`conf`	A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. ISSCC Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2022	—	`conf`	A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. ISSCC Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh
2022	—	`conf`	A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. ISSCC Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2022	—	`conf`	A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. ISSCC Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang
2022	—	`conf`	An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. ISSCC Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2022	J	`jnl`	MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Zuo-Wei Yeh, Zhaofang Li, Chih-Cheng Lu, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang
2022	J	`jnl`	Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. IEEE J. Solid State Circuits Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang
2021	—	`conf`	16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. ISSCC Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2021	J	`jnl`	A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction. IEEE J. Solid State Circuits Tzu-Hsiang Hsu, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh
2021	J	`jnl`	A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel. IEEE J. Solid State Circuits Tzu-Hsiang Hsu, Yen-Kai Chen, Min-Yang Chiu, Guan-Cheng Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh
2021	C	`conf`	A 12-Bit SAR ADC with Reference Voltage Ripple Suppression. ISCAS Wei-Chih Lai, Tzu-Hsiang Hsu, Chih-Cheng Chen, Chih-Cheng Hsieh
2021	—	`conf`	A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter. A-SSCC Chih-Cheng Chen, Chih-Cheng Hsieh
2021	—	`conf`	A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. ISSCC Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2021	—	`conf`	A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model. AICAS Hsin-Yu Wu, Wei-Tse Kao, Harrison Hao-Yu Ku, Cheng-Te Wang, Chih-Cheng Hsieh, Ren-Shuo Liu, Kea-Tiong Tang, Chung-Chuan Lo
2021	J	`jnl`	A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE J. Solid State Circuits Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang
2021	—	`conf`	Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems. AICAS Wen-Chieh Wu, Chen-Fu Yeh, Alexander James White, Cheng-Te Wang, Zuo-Wei Yeh, Chih-Cheng Hsieh, Ren-Shuo Liu, Kea-Tiong Tang, Chung-Chuan Lo
2021	—	`conf`	Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee. ISSCC John Keane, Chih-Cheng Hsieh, Bob Verbruggen
2020	—	`conf`	15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang
2020	—	`conf`	15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. ISSCC Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2020	—	`conf`	15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. ISSCC Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Zhixiao Zhang, Syuan-Hao Sie, Wei-Chen Wei, Yun-Chen Lo, Tai-Hsing Wen, Tzu-Hsiang Hsu, Yen-Kai Chen, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang
2020	—	`conf`	5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel. ISSCC Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh
2020	J	`jnl`	A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si, Ruhui Liu, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Je-Min Hung, Shyh-Shyuan Sheu, Sih-Han Li, Chih-I Wu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2020	C	`conf`	A Monolithic Optical Encoder using CMOS Image Sensor with Background Light Cancellation. ISCAS You-Shin Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, Chih-Cheng Hsieh
2020	J	`jnl`	A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun
2020	J	`jnl`	Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits Cheng-Xin Xue, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Wei-Hao Chen, Meng-Fan Chang, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang
2020	J	`jnl`	MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks. CoRR Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Chih-Cheng Lu, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang
2019	J	`jnl`	A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator. IEEE J. Solid State Circuits Sung-En Hsieh, Chih-Cheng Hsieh
2019	—	`conf`	A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction. A-SSCC Tzu-Hsiang Hsu, Yen-Kai Chen, Tai-Hsing Wen, Wei-Chen Wei, Yi-Ren Chen, Fu-Chun Chang, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh
2019	—	`conf`	A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. ISSCC Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, Chung-Chuan Lo, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2019	C	`conf`	A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting. ISCAS Yung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh
2019	—	`conf`	A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. A-SSCC Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Yen-Cheng Chiu, Je-Min Hong, Shyh-Shyuan Sheu, Sih-Han Li, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2019	J	`jnl`	A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors. IEEE J. Solid State Circuits Kwuang-Han Chang, Chih-Cheng Hsieh
2019	J	`jnl`	A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps. IEEE J. Solid State Circuits Kwuang-Han Chang, Chih-Cheng Hsieh
2019	—	`conf`	A Current-Mode Differential Sensing CMOS Imager for Optical Linear Encoder. VLSI-DAT You-Shin Chen, Tzu-Hsiang Hsu, Chien-Wen Chen, Chih-Cheng Hsieh
2019	—	`conf`	A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang
2019	J	`jnl`	An ULV PWM CMOS Imager With Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting. IEEE J. Solid State Circuits Albert Yen-Chih Chiou, Chih-Cheng Hsieh
2019	—	`conf`	Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices. VLSI Circuits Kea-Tiong Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Chun Kuo, Tai-Hsing Wen, Mon-Shu Ho, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Meng-Fan Chang
2018	J	`jnl`	A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC. IEEE J. Solid State Circuits Sung-En Hsieh, Chih-Cheng Hsieh
2018	—	`conf`	A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator. ISSCC Sung-En Hsieh, Chih-Cheng Hsieh
2018	J	`jnl`	A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization. IEEE J. Solid State Circuits Sung-En Hsieh, Chen-Che Kao, Chih-Cheng Hsieh
2018	J	`jnl`	A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip. IEEE Trans. Circuits Syst. II Express Briefs Ting-I Chou, Kwuang-Han Chang, Jia-Yin Jhang, Shih-Wen Chiu, Guoxing Wang, Chia-Hsiang Yang, Herming Chiueh, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang
2018	J	`jnl`	A 12-bit 150-MS/s Sub-Radix-3 SAR ADC With Switching Miller Capacitance Reduction. IEEE J. Solid State Circuits Kwuang-Han Chang, Chih-Cheng Hsieh
2018	—	`conf`	A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. ISSCC Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2018	—	`conf`	A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections. A-SSCC Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh
2018	J	`jnl`	A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique. IEEE J. Solid State Circuits Tzu-Hsiang Hsu, Ting Liao, Nien-An Lee, Chih-Cheng Hsieh
2018	—	`conf`	A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps. A-SSCC Kwuang-Han Chang, Chih-Cheng Hsieh
2018	—	`conf`	A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array. BioCAS Pin-Yi Li, Cheng-Han Yang, Wei-Hao Chen, Jian-Hao Huang, Wei-Chen Wei, Je-Syu Liu, Wei-Yu Lin, Tzu-Hsiang Hsu, Chih-Cheng Hsieh, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang
2017	J	`jnl`	A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jin-Yi Lin, Chih-Cheng Hsieh
2017	—	`conf`	A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization. A-SSCC Chen-Che Kao, Sung-En Hsieh, Chih-Cheng Hsieh
2017	—	`conf`	A CMOS imaging platform using single photon avalanche diode array in standard technology. IEEE SENSORS Tzu-Hsiang Hsu, Chih-Cheng Hsieh
2017	—	`conf`	A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique. A-SSCC Ting Liao, Nien-An Lee, Chih-Cheng Hsieh
2017	J	`jnl`	A Hybrid Analog-to-Digital Conversion Algorithm With Sub-Radix and Multiple Quantization Thresholds. IEEE Trans. Circuits Syst. I Regul. Pap. Kwuang-Han Chang, Chih-Cheng Hsieh
2016	J	`jnl`	A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Sung-En Hsieh, Chih-Cheng Hsieh
2016	C	`conf`	A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS. ISCAS Sung-En Hsieh, Chih-Cheng Hsieh
2016	J	`jnl`	A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching. IEEE Trans. Circuits Syst. I Regul. Pap. Pei-Chen Lee, Jin-Yi Lin, Chih-Cheng Hsieh
2016	—	`conf`	A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC. VLSI Circuits Sung-En Hsieh, Chih-Cheng Hsieh
2016	C	`conf`	A 0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with input-range-adaptive switching. ISCAS Pei-Chen Lee, Chen-Che Kao, Chih-Cheng Hsieh
2016	—	`conf`	A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS. A-SSCC Kwuang-Han Chang, Chih-Cheng Hsieh
2016	J	`jnl`	A 137 dB Dynamic Range and 0.32 V Self-Powered CMOS Imager With Energy Harvesting Pixels. IEEE J. Solid State Circuits Albert Yen-Chih Chiou, Chih-Cheng Hsieh
2016	J	`jnl`	A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS. IEEE J. Solid State Circuits Yan-Jiun Chen, Kwuang-Han Chang, Chih-Cheng Hsieh
2016	—	`conf`	A hybrid CMOS-imager with perovskites as photoactive layer. IEEE SENSORS Pei-Wen Yen, Yan-Rung Lin, Sheng-Min Yu, Shiu-Cheng Lou, Kai-Ping Chuang, Bor-Nian Chuang, Albert Yen-Chih Chiou, Chih-Cheng Hsieh
2016	—	`conf`	A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetry. A-SSCC Kuan-Lin Liu, Chih-Cheng Hsieh, Sheng-Yeh Lai, Chin-Fong Chiu
2016	—	`conf`	An integrated CMOS optical sensing chip for multiple bio-signal detections. A-SSCC Albert Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng Hsieh
2016	—	`conf`	Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease. BioCAS Ting-I Chou, Shih-Wen Chiu, Kwuang-Han Chang, Yi-Ju Chen, Chen-Ting Tang, Chung-Hung Shih, Chih-Cheng Hsieh, Meng-Fan Chang, Chia-Hsiang Yang, Herming Chiueh, Kea-Tiong Tang
2015	J	`jnl`	A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jin-Yi Lin, Chih-Cheng Hsieh
2015	—	`conf`	A 0.4V self-powered CMOS imager with 140dB dynamic range and energy harvesting. VLSIC Albert Yen-Chih Chiou, Chih-Cheng Hsieh
2015	C	`conf`	A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter. ISCAS Sung-En Hsieh, Cheng-Kang Ho, Chih-Cheng Hsieh
2015	—	`conf`	A 132dB DR readout IC with pulse width modulation for IR focal plane arrays. A-SSCC Chia-Chi Kuo, Chih-Cheng Hsieh
2015	C	`conf`	An 8-bit column-shared SAR ADC for CMOS image sensor applications. ISCAS Jin-Yi Lin, Kwuang-Han Chang, Chen-Che Kao, Shih-Chin Lo, Yan-Jiun Chen, Pei-Chen Lee, Chi-Hui Chen, Chin Yin, Chih-Cheng Hsieh
2015	—	`conf`	An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensor. VLSI-DAT Zheng-Wei Huang, Chin-Fong Chiu, Chih-Cheng Hsieh
2014	—	`conf`	24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia. ISSCC Kea-Tiong Tang, Shih-Wen Chiu, Chung-Hung Shih, Chia-Ling Chang, Chia-Min Yang, Da-Jeng Yao, Jen-Huo Wang, Chien-Ming Huang, Hsin Chen, Kwuang-Han Chang, Chih-Cheng Hsieh, Ting-Hau Chang, Meng-Fan Chang, Chia-Min Wang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu
2014	—	`conf`	A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS. VLSIC Yan-Jiun Chen, Chih-Cheng Hsieh
2014	J	`jnl`	A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia. IEEE Trans. Biomed. Circuits Syst. Shih-Wen Chiu, Jen-Huo Wang, Kwuang-Han Chang, Ting-Hau Chang, Chia-Min Wang, Chia-Lin Chang, Chen-Ting Tang, Chien-Fu Chen, Chung-Hung Shih, Han-Wen Kuo, Li-Chun Wang, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu, Kea-Tiong Tang
2014	—	`conf`	A dual-mode CMOS image sensor for optical wireless communication. VLSI-DAT Chih-Hao Lin, Chih-Cheng Hsieh, Che-Chun Lin, Ren-Jr Chen
2014	—	`conf`	A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array. NEWCAS Shih-Wen Chiu, Jen-Huo Wang, Kwuang-Han Chang, Hsiang-Chiu Wu, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Guoxing Wang, Kea-Tiong Tang
2013	J	`jnl`	2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems. IEEE Trans. Very Large Scale Integr. Syst. Chi-Ying Lee, Chih-Cheng Hsieh, Jenn-Chyou Bor
2013	J	`jnl`	A 0.5 V PWM CMOS Imager With 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise. IEEE J. Solid State Circuits Meng-Ting Chung, Chin-Lin Lee, Chin Yin, Chih-Cheng Hsieh
2013	—	`conf`	A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring. VLSI-DAT Chin Yin, Chih-Cheng Hsieh
2013	—	`conf`	A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS. ISSCC Chang-Yuan Liou, Chih-Cheng Hsieh
2013	J	`jnl`	A 3 Megapixel 100 Fps 2.8 µm Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers. IEEE J. Solid State Circuits Shang-Fu Yeh, Chih-Cheng Hsieh, Ka-Yi Yeh
2012	—	`conf`	A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise. ISSCC Meng-Ting Chung, Chih-Cheng Hsieh
2012	C	`conf`	A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching. ISCAS Hsin-Yuan Huang, Jin-Yi Lin, Chih-Cheng Hsieh, Wen-Hsu Chang, Hann-Huei Tsai, Chin-Fong Chiu
2012	J	`jnl`	Exploration of Second-Order Effects in High-Performance Continuous-Time ΣΔ Modulators Using Discrete-Time Models. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Lin Chen, Chih-Cheng Hsieh
2012	—	`conf`	Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor. VLSI-DAT Kuo-Wei Cheng, Chin Yin, Chih-Cheng Hsieh, Wen-Hsu Chang, Hann-Huei Tsai, Chin-Fong Chiu
2011	C	`conf`	A 0.6V CMOS Image Sensor with in-pixel biphasic current driver for biomedical application. ISCAS Chin-Lin Lee, Chih-Cheng Hsieh
2011	—	`conf`	A 0.8V 64×64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications. A-SSCC Chin-Lin Lee, Chih-Cheng Hsieh
2011	J	`jnl`	A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System. IEEE Trans. Biomed. Circuits Syst. Kea-Tiong Tang, Shih-Wen Chiu, Meng-Fan Chang, Chih-Cheng Hsieh, Jyuo-Min Shyu
2011	—	`conf`	A new CMOS image sensor readout structure for 3D integrated imagers. CICC Shang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh, Ka-Yi Yeh, Chung-Chi Jim Li
2011	C	`conf`	Live demonstration: The prototype of real-time image pre-processing system for satellites' remote sensing. ISCAS Tsan-Jieh Chen, Chih-Hui Weng, Herming Chiueh, Chih-Cheng Hsieh, Shang-Fu Yeh, Wen-Hsu Chang, Ying-Zong Juang, Hann-Huei Tsai, Chin-Fong Chiu
2010	C	`conf`	A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application. ISCAS Sung-Min Chin, Chih-Cheng Hsieh, Chin-Fong Chiu, Hann-Huei Tsai
2009	C	`conf`	A High Performance Linear Current Mode Image Sensor. ISCAS Chih-Cheng Hsieh, Wei-Yu Chen, Chung-Yu Wu
1998	J	`jnl`	High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA. IEEE J. Solid State Circuits Chih-Cheng Hsieh, Chung-Yu Wu, Tai-Ping Sun, Far-Wen Jih, Ya-Tung Cherng
1997	J	`jnl`	A new cryogenic CMOS readout structure for infrared focal plane array. IEEE J. Solid State Circuits Chih-Cheng Hsieh, Chung-Yu Wu, Tai-Ping Sun
1997	J	`jnl`	Focal-plane-arrays and CMOS readout techniques of infrared imaging systems. IEEE Trans. Circuits Syst. Video Technol. Chih-Cheng Hsieh, Chung-Yu Wu, Far-Wen Jih, Tai-Ping Sun