Chih-Chang Lin

18 papers A* 2A 4Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2024 — conf
Exploring User Engagement with Smartwatch Health Services: A Comparative Study Between Taiwan and Singapore.
HCI (17)
Chih-Chang Lin, Fang-Wu Tung, Chien-Hsiung Chen
2020 — conf
Design Guidelines of Social-Assisted Robots for the Elderly: A Mixed Method Systematic Literature Review.
HCI (43)
Chih-Chang Lin, Hao-Yu Liao, Fang-Wu Tung
2019 — conf
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.
CICC
Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin
2019 — conf
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET.
VLSI Circuits
Dirk Pfaff, Shahaboddin Moazzeni, Leisheng Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, Robert Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, Fred Kuo, Wei-Li Chen, Tae Young Goh, Kenny Hsieh
2014 — conf
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS.
ISSCC
Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh
2012 — conf
A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS.
CICC
Tao-Wen Chung, Tsung-Ching Huang, S. Chung, Ming-Chieh Huang, Chih-Chang Lin, Chan-Hong Chern, Fu-Lung Hsueh
1999 J jnl
Logic synthesis for engineering change.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska
1998 A conf
A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.
FPGA
Peichen Pan, Chih-Chang Lin
1998 J jnl
Cost-free scan: a low-overhead scan path design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
1998 J jnl
Test-point insertion: scan paths through functional logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
1997 J jnl
On designing universal logic blocks and their application to FPGA design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Chang Lin, Malgorzata Marek-Sadowska
1996 — conf
Sequential Permissible Functions and their Application to Circuit Optimization.
ED&TC
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee
1996 A* conf
Test Point Insertion: Scan Paths through Combinational Logic.
DAC
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
1995 A conf
Circuit partitioning with logic perturbation.
ICCAD
David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska
1995 A conf
Cost-free scan: a low-overhead scan path design methodology.
ICCAD
Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
1995 A* conf
Logic Synthesis for Engineering Change.
DAC
Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1995 — conf
Logic rectification and synthesis for engineering change.
ASP-DAC
Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
1994 A conf
Universal logic gate for FPGA design.
ICCAD
Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin