Chien-Nan Liu

14 papers A* 1A 5Journal 2Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
Error-Aware Training for In-RRAM Computing Design Considering Non-Ideal Effects in RRAM Crossbar Array and Peripheral Circuits.
ACM J. Emerg. Technol. Comput. Syst.
Shih-Han Chang, Ray-Hong Yen, Chien-Nan Liu
2024 — conf
Mitigating Power and Process Variation for Analog CIM Design Migration.
SMACD
Shih-Han Chang, Shih-Yu Chen, Chun-Wen Yang, Hau-Wei Huang, Yu-cheng Yang, Wei-Liang Chen, Chien-Nan Liu, Hung-Ming Chen
2023 J jnl
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization.
ACM Trans. Design Autom. Electr. Syst.
Ling-Yen Song, Chih-Yun Chou, Tung-Chieh Kuo, Chien-Nan Liu, Juinn-Dar Huang
2022 A conf
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks.
DATE
Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou
2022 — conf
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy.
VLSI-DAT
Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu, Juinn-Dar Huang
2022 A conf
Practical Substrate Design Considering Symmetrical and Shielding Routes.
DATE
Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho
2021 — conf
On Reconfiguring Memory-Centric AI Edge Devices for CIM.
ISOCC
Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
2021 A conf
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design.
DATE
Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou
2021 — conf
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips.
VLSI-DAT
Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu, Juinn-Dar Huang
2020 A conf
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications.
ICCAD
Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
2018 A* conf
Analog placement with current flow and symmetry constraints using PCP-SP.
DAC
Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu
2017 — conf
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering.
VLSI-DAT
Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu
2015 A conf
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).
FPGA
Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He
2008 — conf
A scalable digitalized buffer for gigabit I/O.
CICC
Hungwen Lu, Chauchin Su, Chien-Nan Liu