Chien-In Henry Chen

48 papers A* 1A 2C 6Journal 28Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Dual-Channel Multiframe FFT Processing for Precise Multisignal Detection in Closed-Space RF Environments. IEEE Trans. Instrum. Meas. Kiran Jayarama, Chien-In Henry Chen
2021	J	`jnl`	Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection. Integr. Yu Wang, Jianfeng Ren, Chien-In Henry Chen
2020	J	`jnl`	High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding. Integr. Feiran Liu, Chien-In Henry Chen
2017	J	`jnl`	Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor. VLSI Design Yu Wang, Jian Chen, Chien-In Henry Chen
2016	J	`jnl`	Digital linear chirp receiver for high chirp rates with high resolution time-of-arrival and time-of-departure estimation. IEEE Trans. Aerosp. Electron. Syst. Stephen Benson, Chien-In Henry Chen, David M. Lin, Lihyeh L. Liou
2015	J	`jnl`	Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection. VLSI Design Jian Chen, Chien-In Henry Chen
2014	—	`conf`	Modular test RF instrumentation and measurement for a hybrid computing digital wideband receiver. I2MTC Kiran George, Chien-In Henry Chen
2013	J	`jnl`	Multiple Signal Detection Digital Wideband Receiver using Hardware Accelerators. IEEE Trans. Aerosp. Electron. Syst. Kiran George, Chien-In Henry Chen
2011	J	`jnl`	A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement. IEEE Trans. Instrum. Meas. Kiran George, Chien-In Henry Chen
2011	J	`jnl`	Adaptive Thresholding for High Dual-Tone Signal Instantaneous Dynamic Range in Digital Microwave Receiver. IEEE Trans. Instrum. Meas. Stephen Benson, Chien-In Henry Chen
2011	—	`conf`	Delay optimization considering power saving in dynamic CMOS circuits. ISQED Kumar Yelamarthi, Chien-In Henry Chen
2010	J	`jnl`	Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations. VLSI Design Kumar Yelamarthi, Chien-In Henry Chen
2009	C	`conf`	Dual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme. ISCAS Yu-Heng George Lee, Chien-In Henry Chen
2009	J	`jnl`	Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection. IEEE Trans. Instrum. Meas. Yu-Heng George Lee, Chien-In Henry Chen
2009	J	`jnl`	Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip. IEEE Trans. Instrum. Meas. Kiran George, Chien-In Henry Chen
2008	—	`conf`	FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver. ISQED James Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui
2008	—	`conf`	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ISQED Kumar Yelamarthi, Chien-In Henry Chen
2008	J	`jnl`	Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. J. Comput. Kumar Yelamarthi, Chien-In Henry Chen
2008	C	`conf`	Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver. ISCAS Yu-Heng George Lee, James Helton, Chien-In Henry Chen
2008	J	`jnl`	Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test. IEEE Trans. Instrum. Meas. Xinhui Zhang, Chien-In Henry Chen, Arvindkumar Chakravarthy
2007	J	`jnl`	Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. Jason Wibbenmeyer, Chien-In Henry Chen
2007	J	`jnl`	Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS. IEEE Trans. Instrum. Meas. Mingzhen Wang, Chien-In Henry Chen, Shailesh Radhakrishnan
2007	—	`conf`	Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications. SoCC Mingzhen Wang, Chien-In Henry Chen
2007	—	`conf`	Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. ISQED Kumar Yelamarthi, Chien-In Henry Chen
2005	—	`conf`	A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder. ISCAS (6) Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen
2005	J	`jnl`	Design and performance evaluation of a 2.5-GSPS digital receiver. IEEE Trans. Instrum. Meas. Chien-In Henry Chen, Kiran George, William McCormick, James B. Y. Tsui, Stephen L. Hary, Keith M. Graves
2004	J	`jnl`	Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test. IEEE Trans. Instrum. Meas. Chien-In Henry Chen, Kiran George
2003	—	`conf`	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. ISQED Chien-In Henry Chen, Kiran George
2003	—	`conf`	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. ISCAS (5) Chien-In Henry Chen, Kiran George
2002	J	`jnl`	Testability Synthesis for Jumping Carry Adders. VLSI Design Chien-In Henry Chen, Mahesh Wagh
2002	J	`jnl`	Timing Analysis and Optimization for DSM IC - Guest Editorial. VLSI Design Chien-In Henry Chen
2002	J	`jnl`	Timing Challenges for Very Deep Sub-Micron (VDSM) IC. VLSI Design Ichiang Lin, Chien-In Henry Chen
2002	J	`jnl`	Timing-Driven-Testable Convergent Tree Adders. VLSI Design Johnnie A. Huang, Chien-In Henry Chen
2001	—	`conf`	Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults. ISSS Chien-In Henry Chen
2000	J	`jnl`	Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs. VLSI Design Chien-In Henry Chen, Yingjie Zhou
1999	—	`conf`	High-level design synthesis with redundancy removal for high speed testable adders. ISCAS (6) Meghanad D. Wagh, Chien-In Henry Chen
1994	J	`jnl`	Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design. IEEE Trans. Very Large Scale Integr. Syst. Chien-In Henry Chen, Joel T. Yuen
1994	J	`jnl`	Cluster Partitioning Techniques for Data Path Synthesis. VLSI Design Chien-In Henry Chen, Gerald E. Sobelman
1994	J	`jnl`	Comments on "Area-Time Optimal Adder Design". IEEE Trans. Computers Chien-In Henry Chen, Anup Kumar
1994	J	`jnl`	Partitioning Techniques for Built-In Self-Test Design. VLSI Design Chien-In Henry Chen
1994	J	`jnl`	Using PDM on Multiport Memory Allocation in Data Path. VLSI Design Chien-In Henry Chen
1993	A	`conf`	Logic partitioning to pseudo-exhaustive test for BIST design. ICCAD Chien-In Henry Chen, Joel T. Yuen
1992	C	`conf`	Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment. ICCD Chien-In Henry Chen, Joel T. Yuen, Ji-Der Lee
1992	C	`conf`	Concurrent Test Scheduling in Built-In Self-Test Environment. ICCD Chien-In Henry Chen, Joel T. Yuen
1991	C	`conf`	Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis. ICCD Chien-In Henry Chen
1991	A	`conf`	BISTSYN - A Built-In Self-Test Synthesizer. ICCAD Chien-In Henry Chen
1991	A*	`conf`	Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit. DAC Chien-In Henry Chen
1989	C	`conf`	An efficient approach to pseudo-exhaustive test generation for BIST design. ICCD Chien-In Henry Chen, Gerald E. Sobelman