Chien-Hsing Wu

16 papers C 1Misc 1Journal 4Unranked 10
YearRankTypeTitle / Venue / Authors
2017 J jnl
Robust Training Symbol Assisted Least Squares Estimation for Direct Conversion Receivers with Oscillator IQ-Imbalance.
Wirel. Pers. Commun.
Chia-Peng Chou, Tsung-Hsien Liu, Chien-Hsing Wu
2009 — conf
Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing.
ICC
Chia-Peng Chou, Chien-Hsing Wu, Tsung-Hsien Liu, Yin-Tsung Hwang
2005 — conf
Quantum circuits for stabilizer codes.
ISCAS (3)
Chien-Hsing Wu, Yan-Chr Tsai, Hwa-Long Tsai
2005 J jnl
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen
2004 J jnl
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
IEEE Trans. Computers
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
2004 — conf
VLSI architecture exploration for sliding-window Log-MAP decoders.
ISCAS (2)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo
2003 — conf
FPGA realization of an OFDM frame synchronization design for dispersive channels.
ISCAS (2)
Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu
2002 — conf
An area-efficient systolic division circuit over GF(2
ISCAS (5)
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
2002 — conf
Memory arrangements in turbo decoders using sliding-window BCJR algorithm.
ISCAS (5)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
2002 J jnl
Novel Algorithms and VLSI Design for Division over GF(2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
2001 — conf
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
ISCAS (4)
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
2001 — conf
VLSI architecture of extended in-place path metric update for Viterbi decoders.
ISCAS (4)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
2000 C conf
An efficient approach for in-place scheduling of path metric update in Viterbi decoders.
ISCAS
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
1999 — conf
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.
ISCAS (1)
Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu
1999 — conf
An area-efficient versatile Reed-Solomon decoder for ADSL.
ISCAS (1)
Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
1995 Misc conf
Design of an MPEG-based set-top box for video on demand services.
ICASSP
Yin-Hwa Huang, Yuo-Chuan Chang, Chi-Shyan Wu, Chien-Hsing Wu