Chien-Heng Wong

12 papers A* 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2019 — conf
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.
NOCS
Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang
2018 J jnl
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
X. Shawn Wang, Xin Jin, Jieqiong Du, Yilei Li, Yuan Du, Chien-Heng Wong, Yen-Cheng Kuan, Chi-Hang Chan, Mau-Chung Frank Chang
2018 J jnl
A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yilei Li, Kirti Dhwaj, Chien-Heng Wong, Yuan Du, Li Du, Yiwu Tang, Yiyu Shi, Tatsuo Itoh, Mau-Chung Frank Chang
2018 — conf
A fully integrated 28nm CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mv startup voltage.
CICC
Yiwu Tang, Chien-Heng Wong, Yuan Du, Li Du, Yilei Li, Mau-Chung Frank Chang
2017 J jnl
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection.
IEEE J. Solid State Circuits
Yuan Du, Wei-Han Cho, Po-Tsang Huang, Yilei Li, Chien-Heng Wong, Jieqiong Du, Yanghyo Kim, Boyu Hu, Li Du, Chun-Chen Liu, Sheau Jiung Lee, Mau-Chung Frank Chang
2017 J jnl
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers.
IEEE J. Solid State Circuits
Zuow-Zun Chen, Yen-Cheng Kuan, Yilei Li, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang
2016 — conf
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
ISSCC
Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2016 — conf
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS.
VLSI Circuits
Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang
2016 J jnl
A 200-MS/s Phase-Detector-Based Comparator With 400-μV
IEEE Trans. Circuits Syst. II Express Briefs
Chin-Yu Lin, Chien-Heng Wong, Chia-Hau Hsu, Yen-Hsin Wei, Tai-Cheng Lee
2016 — conf
Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers.
VLSI Circuits
Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang
2016 A* conf
Invited - A 2.2 GHz SRAM with high temperature variation immunity for deep learning application under 28nm.
DAC
Chun-Chen Liu, Yen-Hsiang Wang, Yilei Li, Chien-Heng Wong, Tien Pei Chou, Young-Kai Chen, M.-C. Frank Chang
2013 J jnl
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chien-Heng Wong, Tai-Cheng Lee