Chien-Ching Lin

15 papers C 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2010 J jnl
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
IEEE J. Solid State Circuits
Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
2009 J jnl
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee
2009 J jnl
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 C conf
Multi-mode message passing switch networks applied for QC-LDPC decoder.
ISCAS
Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua
2007 — conf
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.
CICC
Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su
2007 J jnl
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Terng-Ren Hsu, Chien-Ching Lin, Terng-Yin Hsu, Chen-Yi Lee
2007 J jnl
Self-Compensation Technique for Simplified Belief-Propagation Algorithm.
IEEE Trans. Signal Process.
Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu
2006 — conf
A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications.
ISSCC
Lei-Fone Chen, Yuan Chen, Lu-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee
2006 J jnl
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2005 — conf
A 3.33Gb/s (1200,720) low-density parity check code decoder.
ESSCIRC
Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee
2005 J jnl
Design of a power-reduction Viterbi decoder for WLAN applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2004 — conf
A dual mode channel decoder for 3GPP2 mobile wireless communications.
ESSCIRC
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2004 — conf
A power and area efficient multi-mode FEC processor.
ISCAS (2)
Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
2004 — conf
Multi-level memory systems using error control codes.
ISCAS (2)
Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
2003 — conf
A low power and high speed Viterbi decoder chip for WLAN applications.
ESSCIRC
Chien-Ching Lin, Chia-Cho Wu, Chen-Yi Lee