Chia Yee Ooi - RankMe

46 papers B 1C 9Misc 2Journal 20Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Review of Machine Learning and Deep Learning Trends in EEG-Based Epileptic Seizure Prediction. IEEE Access Yitong Wu, Eileen Lee Ming Su, Mingyu Wu, Chia Yee Ooi, William Holderbaum
2025	J	`jnl`	In-Depth Review and Comparative Analysis of DRAM-Based PUFs. IEEE Access Yuin Yee Chew, Wei Liang Lim, Jun Liang Tan, Chia Yee Ooi
2022	—	`conf`	An FPGA-based IP Core Subscription-Oriented Fog Computing Platform. IPDPS Workshops Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
2022	J	`jnl`	Efficient hardware-accelerated pseudoinverse computation through algorithm restructuring for parallelization in high-level synthesis. Int. J. Circuit Theory Appl. Chong Yeam Tan, Chia Yee Ooi, Hau Sim Choo, Nordinah Ismail
2022	J	`jnl`	RtFog: A Real-Time FPGA-Based Fog Node With Remote Dynamically Reconfigurable Application Plane for Fog Analytics Redeployment. IEEE Trans. Green Commun. Netw. Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono
2022	J	`jnl`	Use of learning approaches to predict clinical deterioration in patients based on various variables: a review of the literature. Artif. Intell. Rev. Tariq Ibrahim Al-Shwaheen, Mehrdad Moghbel, Yuan Wen Hau, Chia Yee Ooi
2021	C	`conf`	An FPGA-based Middlebox with Remote Dynamically Reconfigurable Application Plane. TENCON Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
2020	J	`jnl`	A review of breast boundary and pectoral muscle segmentation methods in computer-aided detection/diagnosis of breast mammography. Artif. Intell. Rev. Mehrdad Moghbel, Chia Yee Ooi, Nordinah Ismail, Yuan Wen Hau, Nogol Memari
2020	J	`jnl`	Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Chee Hoo Kok
2019	C	`conf`	Classification of Trojan Nets Based on SCOAP Values using Supervised Learning. ISCAS Chee Hoo Kok, Chia Yee Ooi, Mehrdad Moghbel, Nordinah Ismail, Hau Sim Choo, Michiko Inoue
2019	—	`conf`	Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security. IRICT Pyi Phyo Aung, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi
2019	—	`conf`	Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis. SoCC Chong Yeam Tan, Chia Yee Ooi, Nordinah Ismail
2019	—	`conf`	Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level. ATS Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, Fawnizu Azmadi Hussin
2019	—	`conf`	Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection. ATS Chee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, Nordinah Ismail, Fawnizu Azmadi Hussin
2018	—	`conf`	drDRM: A PUF-Based Dynamically Reconfigurable DRM Mechanism for FPGA-Based Platform. CANDAR Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono
2017	J	`jnl`	An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue
2017	J	`jnl`	Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms. J. Syst. Archit. Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono
2017	J	`jnl`	Ping-lock round robin arbiter. Microelectron. J. Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, Muhammad N. Marsono
2017	—	`conf`	hpFog: A FPGA-Based Fog Computing Platform. NAS Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono
2016	—	`conf`	A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler. FPT Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
2016	—	`conf`	Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. NoCArc@MICRO Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, Maurizio Palesi
2016	C	`conf`	Power-aware through-silicon-via minimization by partitioning finite state machine with datapath. ISCAS Ayub Chin Abdullah, Chia Yee Ooi, Nordinah Bt Ismail, Nurita Binti Mohammad
2016	C	`conf`	SVA checker generator for FPGA-based verification platform. ISCAS Nurita Mohamad, Chia Yee Ooi, Nordinah Bt Ismail, Jwing Teh
2015	J	`jnl`	A Novel Scan Architecture for Low Power Scan-Based Testing. VLSI Design Mahshid Mojtabavi Naeini, Chia Yee Ooi
2015	Misc	`conf`	Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms. FCCM Jeevan Sirkunan, Chia Yee Ooi, Muhammad N. Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono
2015	J	`jnl`	Built-in Self Test Power and Test Time Analysis in On-chip Networks. Circuits Syst. Signal Process. Mahdieh Nadi Senejani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad Nadzir Marsono
2015	J	`jnl`	Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique. Int. J. Reconfigurable Comput. Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono
2015	Misc	`conf`	Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers. FCCM Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono
2015	B	`conf`	rrBox: A remote dynamically reconfigurable network processing middlebox. FPL Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
2014	C	`conf`	Hardware transactional memory on multi-processor FPGA platform. ISCAS Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad Nadzir Marsono
2014	C	`conf`	Packet logging mechanism for adaptive online fault detection on Network-on-Chip. ISCAS Ling Kim Loo, Chia Yee Ooi, V. Y. Liew, Yuan Wen Hau, Muhammad N. Marsono
2014	C	`conf`	Remote dynamically reconfigurable platform using NetFPGA. ISCAS Tze Hon Tan, Chia Yee Ooi, Yuan Wen Hau, Nasir Shaikh-Husin, Muhammad N. Marsono
2014	J	`jnl`	Thermal Model with Metal Consideration for System-on-Chip Testing. J. Low Power Electron. Hasliza Hassan, Chia Yee Ooi
2014	—	`conf`	rrBox: A Remote Dynamically Reconfigurable Middlebox for Network Protection. CANDAR Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
2014	—	`conf`	rrBox: Remote dynamically reconfigurable middlebox using NetFPGA. ISCIT Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
2013	J	`jnl`	A Semi-Analytical Approach to Study the Energy Consumption of On-Chip Networks Testing. J. Low Power Electron. Mahdieh Nadi Senjani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad N. Marsono
2013	C	`conf`	Feasible transition path generation for EFSM-based system testing. ISCAS Sieng Wong, Chia Yee Ooi, Yuan Wen Hau, Muhammad N. Marsono, Nasir Shaikh-Husin
2012	J	`jnl`	Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm. Comput. Electr. Eng. Chia Yee Ooi, Jia Pao Sua, Siaw Chen Lee
2011	—	`conf`	A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip. ASICON Yuan Wen Hau, Muhammad N. Marsono, Chia Yee Ooi, Mohamed Khalil Hani
2011	J	`jnl`	A New Design-for-Testability Method Based on Thru-Testability. J. Electron. Test. Chia Yee Ooi, Hideo Fujiwara
2008	J	`jnl`	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
2007	J	`jnl`	Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tau IEICE Trans. Inf. Syst. Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
2006	C	`conf`	A New Class of Sequential Circuits with Acyclic Test Generation Complexity. ICCD Chia Yee Ooi, Hideo Fujiwara
2006	—	`conf`	A New Scan Design Technique Based on Pre-Synthesis Thru Functions. ATS Chia Yee Ooi, Hideo Fujiwara
2005	J	`jnl`	Classification of Sequential Circuits Based on tau IEICE Trans. Inf. Syst. Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
2004	—	`conf`	Classification of Sequential Circuits Based on ?k Notation. Asian Test Symposium Chia Yee Ooi, Hideo Fujiwara