Chia-Yu Hsu

14 papers Misc 1Journal 13
YearRankTypeTitle / Venue / Authors
2024 J jnl
Guest editorial: Value chain collaboration for complicated product innovation and manufacturing excellence by industrial data-driven modeling and optimization.
Ind. Manag. Data Syst.
Runliang Dou, Kuo-Yi Lin, Chia-Yu Hsu, Mohammad T. Khasawneh
2024 J jnl
Value co-creation in group enterprises: an evolutionary game theory-based analysis.
Int. J. Prod. Res.
Runliang Dou, Guofang Nan, Ziqian Wei, Chia-Yu Hsu
2021 J jnl
Applications of new industrial engineering methodologies.
Comput. Ind. Eng.
Qiuhong Zhao, Runliang Dou, Kuo-Yi Lin, Chia-Yu Hsu
2018 J jnl
Foreword: Smart manufacturing, innovative product and service design to empower Industry 4.0.
Comput. Ind. Eng.
Runliang Dou, Zhen He, Chia-Yu Hsu
2018 J jnl
Industry Applications of Computational Intelligence: Preface.
Int. J. Comput. Intell. Syst.
Runliang Dou, Chen-Fu Chien, Imed Kacem, Chia-Yu Hsu
2016 J jnl
Semiconductor manufacturing intelligence and automation.
Comput. Ind. Eng.
Chen-Fu Chien, Chia-Yu Hsu, James R. Morrison, Runliang Dou
2015 J jnl
A novel approach to hedge and compensate the critical dimension variation of the developed-and-etched circuit patterns for yield enhancement in semiconductor manufacturing.
Comput. Oper. Res.
Chen-Fu Chien, Ying-Jen Chen, Chia-Yu Hsu
2014 J jnl
Manufacturing intelligence and innovation for digital manufacturing and operational excellence.
J. Intell. Manuf.
Chen-Fu Chien, Mitsuo Gen, Yongjiang Shi, Chia-Yu Hsu
2014 J jnl
Overlay Error Compensation Using Advanced Process Control With Dynamically Adjusted Proportional-Integral R2R Controller.
IEEE Trans Autom. Sci. Eng.
Chen-Fu Chien, Ying-Jen Chen, Chia-Yu Hsu, Hung-Kai Wang
2013 J jnl
Overall Wafer Effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole.
Comput. Ind. Eng.
Chen-Fu Chien, Chia-Yu Hsu, Kuo-Hao Chang
2012 J jnl
Manufacturing intelligence to forecast and reduce semiconductor cycle time.
J. Intell. Manuf.
Chen-Fu Chien, Chia-Yu Hsu, Chih-Wei Hsiao
2011 Misc conf
Manufacturing intelligence for determining machine subgroups to enhance yield in semiconductor manufacturning.
WSC
Chen-Fu Chien, Ying-Jen Chen, Chia-Yu Hsu, Yi-Hao Yeh
2011 J jnl
UNISON analysis to model and reduce step-and-scan overlay errors for semiconductor manufacturing.
J. Intell. Manuf.
Chen-Fu Chien, Chia-Yu Hsu
2006 J jnl
A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing.
J. Intell. Manuf.
Chen-Fu Chien, Chia-Yu Hsu