Chia-Tung Ho - RankMe

36 papers A* 2A 3Journal 20Unranked 10

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation. CoRR Dimple Vijay Kochar, Nathaniel Ross Pinckney, Guan-Ting Liu, Chia-Tung Ho, Chenhui Deng, Haoxing Ren, Brucek Khailany
2026	—	`conf`	Invited: Polymath: Self-Improving Hierarchical Workflow for Multi-Domain Problem Solving. ISPD Chia-Tung Ho, Jing Gong, Haoyu Yang, Abhishek B. Akkur, Haoxing Ren
2026	J	`jnl`	LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generation. CoRR Hejia Zhang, Zhongming Yu, Chia-Tung Ho, Haoxing Ren, Brucek Khailany, Jishen Zhao
2025	—	`conf`	ASPEN: LLM-Guided E-Graph Rewriting for RTL Datapath Optimization. MLCAD Niansong Zhang, Chenhui Deng, Johannes Maximilian Kühn, Chia-Tung Ho, Cunxi Yu, Zhiru Zhang, Haoxing Ren
2025	J	`jnl`	Autonomous Code Evolution Meets NP-Completeness. CoRR Cunxi Yu, Rongjian Liang, Chia-Tung Ho, Haoxing Ren
2025	A	`conf`	ChipVQA: Benchmarking Visual Language Models for Chip Design. DATE Haoyu Yang, Qijing Huang, Nathaniel Ross Pinckney, Walker J. Turner, Wenfei Zhou, Yanqing Zhang, Chia-Tung Ho, Chen-Chia Chang, Haoxing Ren
2025	J	`jnl`	Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification. CoRR Nathaniel Ross Pinckney, Chenhui Deng, Chia-Tung Ho, Yun-Da Tsai, Mingjie Liu, Wenfei Zhou, Brucek Khailany, Haoxing Ren
2025	—	`conf`	DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent. ISPD Chen-Chia Chang, Chia-Tung Ho, Yaguang Li, Yiran Chen, Haoxing Ren
2025	J	`jnl`	FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures. CoRR Yunsheng Bai, Ghaith Bany Hamad, Chia-Tung Ho, Syed Suhaib, Haoxing Ren
2025	J	`jnl`	HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization. CoRR Souradip Poddar, Chia-Tung Ho, Ziming Wei, Weidong Cao, Haoxing Ren, David Z. Pan
2025	J	`jnl`	Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design. CoRR Chia-Tung Ho, Jing Gong, Yunsheng Bai, Chenhui Deng, Haoxing Ren, Brucek Khailany
2025	J	`jnl`	PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification. CoRR Yujie Zhao, Zhijing Wu, Hejia Zhang, Zhongming Yu, Wentao Ni, Chia-Tung Ho, Haoxing Ren, Jishen Zhao
2025	J	`jnl`	Polymath: A Self-Optimizing Agent with Dynamic Hierarchical Workflow. CoRR Chia-Tung Ho, Jing Gong, Xufeng Yao, Yunsheng Bai, Abhishek B. Akkur, Haoxing Ren
2025	J	`jnl`	SchemaCoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting. CoRR Lily Jiaxin Wan, Chia-Tung Ho, Rongjian Liang, Cunxi Yu, Deming Chen, Haoxing Ren
2025	J	`jnl`	Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph. CoRR Jatin Nainani, Chia-Tung Ho, Anirudh Dhurka, Haoxing Ren
2025	A*	`conf`	VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool. AAAI Chia-Tung Ho, Haoxing Ren, Brucek Khailany
2024	A*	`conf`	DGR: Differentiable Global Router. DAC Wei Li, Rongjian Liang, Anthony Agnesina, Haoyu Yang, Chia-Tung Ho, Anand Rajaram, Haoxing Ren
2024	J	`jnl`	DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent. CoRR Chen-Chia Chang, Chia-Tung Ho, Yaguang Li, Yiran Chen, Haoxing Ren
2024	J	`jnl`	Large Language Model (LLM) for Standard Cell Layout Design Optimization. CoRR Chia-Tung Ho, Haoxing Ren
2024	—	`conf`	Novel Transformer Model Based Clustering Method for Standard Cell Design Automation. ISPD Chia-Tung Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Haoxing Ren
2024	—	`conf`	ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis. MLCAD Rongjian Liang, Chia-Tung Ho, Anthony Agnesina, Wen-Hao Liu, Haoxing Ren
2024	J	`jnl`	VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool. CoRR Chia-Tung Ho, Haoxing Ren, Brucek Khailany
2023	—	`conf`	NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. ISPD Chia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren
2022	J	`jnl`	Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin
2022	J	`jnl`	Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. IEEE Access Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin
2022	—	`conf`	Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. ASP-DAC Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz
2022	J	`jnl`	Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. CoRR Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz
2022	—	`—`	Novel Computer Aided Design (CAD) Methodology for Emerging Technologies to Fight the Stagnation of Moore's Law Chia-Tung Ho
2021	J	`jnl`	Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. IEEE Trans. Very Large Scale Integr. Syst. Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park
2021	—	`conf`	Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning. SLIP Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin
2021	J	`jnl`	SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2020	A	`conf`	A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. ICCAD Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park
2019	A	`conf`	IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. ICCAD Chia-Tung Ho, Andrew B. Kahng
2017	J	`jnl`	InTraSim: Incremental Transient Simulation of Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Min Lee, Chia-Tung Ho
2014	—	`conf`	Incremental transient simulation of power grid. ISPD Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng
2013	—	`conf`	Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. VLSI-DAT Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng