Chia-Sheng Wen

13 papers C 2Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2017 J jnl
Hierarchical Multipartite Function Evaluation.
IEEE Trans. Computers
Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang
2015 J jnl
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation.
IEEE Trans. Circuits Syst. II Express Briefs
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher
2014 C conf
Compression of Lookup Table for Piecewise Polynomial Function Evaluation.
DSD
Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu
2013 J jnl
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping.
IEEE Trans. Very Large Scale Integr. Syst.
Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen
2013 — conf
Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units.
VLSI-DAT
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen
2012 — conf
Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system.
APCCAS
Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen
2012 — conf
Low-cost designs of rectangular to polar coordinate converters for digital communication.
APCCAS
Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee
2012 J jnl
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions.
IEEE Trans. Circuits Syst. II Express Briefs
Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen
2010 — conf
Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method.
APCCAS
Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen
2010 J jnl
Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment.
IEEE Trans. Circuits Syst. II Express Briefs
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
2008 C conf
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.
ISCAS
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
2006 — conf
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.
APCCAS
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
2005 — conf
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.
ISCAS (3)
Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen