Chia-Lin Yang

127 papers A* 19A 30B 6C 3Misc 7Journal 38Unranked 24
YearRankTypeTitle / Venue / Authors
2026 J jnl
CIMNet: Joint Search for Neural Network and Computing-in-Memory Architectures.
IEEE Micro
Xuan-Jun Chen, Chia-Lin Yang
2025 A conf
Accelerating Genome Alignment Pipeline with In-NAND Search Technology and Group Testing Techniques.
ICCAD
Ming-Hsiang Tsai, Ming-Liang Wei, Chia-Chun Chien, Po-Hao Tseng, Yung-Chun Lee, Hsiang-Pang Li, Chia-Lin Yang
2025 J jnl
Capacitor Minimization in Analog Synapses for Efficient and Compact Binarized SNNs.
IEEE Trans. Circuits Syst. Artif. Intell.
Mikail Yayla, Ming-Liang Wei, Simon Thomann, Albi Mema, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch
2025 A conf
Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices.
DATE
Jing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang
2025 — conf
In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis.
ASP-DAC
You-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li
2025 A conf
REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based Attacks.
DATE
Hassan Nassar, Ming-Liang Wei, Chia-Lin Yang, Jörg Henkel, Kuan-Hsun Chen
2025 J jnl
Resilient Endurance-Aware NVM-based PUF against Learning-based Attacks.
CoRR
Hassan Nassar, Ming-Liang Wei, Chia-Lin Yang, Jörg Henkel, Kuan-Hsun Chen
2024 A conf
Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications.
ICCAD
Jörg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Taylan Seidl, Kuan-Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, Ming-Liang Wei
2024 A* conf
PointCIM: A Computing-in-Memory Architecture for Accelerating Deep Point Cloud Analytics.
MICRO
Xuan-Jun Chen, Han-Ping Chen, Chia-Lin Yang
2024 Misc conf
RecTS: A Temporal-Aware Memory System Optimization for Training Deep Learning Recommendation Models.
SYSTOR
Cheng-Yu Chen, Jui-Nan Yen, You-Ru Lai, Yun-Ping Lin, Chia-Lin Yang
2023 J jnl
HW/SW Codesign for Robust and Efficient Binarized SNNs by Capacitor Minimization.
CoRR
Mikail Yayla, Simon Thomann, Ming-Liang Wei, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch
2023 J jnl
Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing Machine With In-Situ Synapse Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Hussam Amrouch, Chia-Lin Yang
2023 Misc conf
Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories.
VTS
Mikail Yayla, Simon Thomann, Md. Mazharul Islam, Ming-Liang Wei, Shu-Yin Ho, Ahmedullah Aziz, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch
2023 Misc conf
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.
CASES
Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
2023 A* conf
Tensor Movement Orchestration in Multi-GPU Training Systems.
HPCA
Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang
2023 J jnl
Understanding Computer Architecture Sustainability.
Computer
Chia-Lin Yang
2023 A* conf
Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical Isometry.
DAC
Xuan-Jun Chen, Cynthia Kuan, Chia-Lin Yang
2022 J jnl
A Forward Speculative Interference Attack.
Computer
Chia-Lin Yang
2022 J jnl
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators.
ACM Trans. Embed. Comput. Syst.
Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien
2022 A* conf
Efficient Bad Block Management with Cluster Similarity.
HPCA
Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo
2022 — conf
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging.
NVMSA
Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li
2022 — conf
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support.
ASP-DAC
Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang
2022 A* conf
RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference.
HPCA
Xuan Sun, Hu Wan, Qiao Li, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue
2022 — conf
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator.
ASP-DAC
Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai
2021 C conf
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads.
ISCAS
Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien
2021 J jnl
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads.
CoRR
Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien
2021 B conf
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning.
ISPASS
Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-wei Huang
2021 A conf
Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization.
ICCAD
Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Chia-Lin Yang, Hussam Amrouch
2021 — conf
FlashEmbedding: storing embedding tables in SSD for large-scale recommender systems.
APSys
Hu Wan, Xuan Sun, Yufei Cui, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue
2021 A conf
Future Computing Platform Design: A Cross-Layer Design Approach.
DATE
Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo
2021 — conf
Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses.
IRPS
Ming-Liang Wei, Hussam Amrouch, Cheng-Lin Sung, Hang-Ting Lue, Chia-Lin Yang, Keh-Chung Wang, Chih-Yuan Lu
2021 J jnl
ezGeno: an automatic model selection package for genomic data analysis.
Bioinform.
Jun-Liang Lin, Tsung-Ting Hsieh, Yi-An Tung, Xuan-Jun Chen, Yu-Chun Hsiao, Chia-Lin Yang, Tyng-Luh Liu, Chien-Yu Chen
2020 A* conf
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.
DAC
Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li
2019 — conf
Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.
NVMSA
Cheng Ji, Lun Wang, Qiao Li, Congming Gao, Liang Shi, Chia-Lin Yang, Chun Jason Xue
2019 B conf
Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge Devices.
ICIP
Chien-I Lee, Meng-Yao Lin, Chia-Lin Yang, Yen-Kuang Chen
2019 A* conf
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks.
ISCA
Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li
2019 A conf
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper.
ICCAD
Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang
2018 A* conf
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures.
DAC
Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang
2018 A conf
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.
ICCAD
Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang
2018 J jnl
LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling.
CoRR
Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang
2017 J jnl
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration.
ACM Trans. Design Autom. Electr. Syst.
Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang
2017 B conf
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.
ISPASS
Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung
2017 — conf
Enabling fast preemption via Dual-Kernel support on GPUs.
ASP-DAC
Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang
2017 J jnl
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives.
IEEE Trans. Computers
Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang
2017 J jnl
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling.
IEEE Comput. Archit. Lett.
Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang
2017 A* conf
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach.
DAC
Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang
2017 A conf
Message from the general co-chairs.
ISLPED
David Garrett, Chia-Lin Yang
2017 J jnl
Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED).
IEEE Des. Test
David Garrett, Chia-Lin Yang
2016 J jnl
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality.
IEEE Trans. Computers
Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
2016 A* conf
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.
DAC
Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang
2016 — conf
MCSSim: A memory channel storage simulator.
ASP-DAC
Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li
2015 — conf
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
NVMSA
Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang
2015 A conf
Fine-grained write scheduling for PCM performance improvement under write power budget.
ISLPED
Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li
2015 A* conf
Improving DRAM latency with dynamic asymmetric subarray.
MICRO
Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang
2015 J jnl
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs.
ACM Trans. Archit. Code Optim.
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
2015 J jnl
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach.
ACM Trans. Embed. Comput. Syst.
Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-wen Hsueh, Naehyuck Chang
2015 — conf
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.
RACS
Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu
2014 A* conf
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.
DAC
Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
2014 — conf
Full system simulation framework for integrated CPU/GPU architecture.
VLSI-DAT
Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky
2014 J jnl
Guest Editors' Introduction: Cloud Computing for Embedded Systems.
IEEE Des. Test
Martin Dimitrov, Yung-Hsiang Lu, Chia-Lin Yang
2014 A* conf
NVM duet: unified working memory and persistent store architecture.
ASPLOS
Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-Yuan Michael Wang
2013 A* conf
DuraCache: a durable SSD cache using MLC NAND flash.
DAC
Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen
2013 A conf
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.
ISLPED
Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu
2013 — conf
Thermal coupling aware task migration using neighboring core search for many-core systems.
VLSI-DAT
Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
2012 B conf
A cycle-level SIMT-GPU simulation framework.
ISPASS
Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng
2012 A* conf
Age-based PCM wear leveling with nearly zero search cost.
DAC
Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang
2012 A conf
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.
ICCAD
Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen
2012 — conf
Memory access aware power gating for MPSoCs.
ASP-DAC
Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang
2012 A conf
Optimizing NAND flash-based SSDs via retention relaxation.
FAST
Ren-Shuo Liu, Chia-Lin Yang, Wei Wu
2012 C conf
SECRET: Selective error correction for refresh energy reduction in DRAMs.
ICCD
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
2011 — conf
A SAT-based routing algorithm for cross-referencing biochips.
SLIP
Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang
2011 J jnl
A Study of a Heuristic Capacity Planning Algorithm for Weapon Production System.
Int. J. Electron. Bus. Manag.
James C. Chen, Kou-Huang Chen, Chien-Hsin Lin, Chia-Wen Chen, Chia-Lin Yang
2011 J jnl
Power gating strategies on GPUs.
ACM Trans. Archit. Code Optim.
Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng
2011 J jnl
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems.
IEEE Trans. Computers
Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen
2011 J jnl
Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
2010 A conf
Dynamic thermal management for networked embedded systems under harsh ambient temperature variation.
ISLPED
Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang
2010 A conf
Hierarchical memory scheduling for multimedia MPSoCs.
ICCAD
Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang
2010 A* conf
Memory Latency Reduction via Thread Throttling.
MICRO
Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang
2010 A conf
PM-COSYN: PE and memory co-synthesis for MPSoCs.
DATE
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
2010 — conf
Parallelization and characterization of GARCH option pricing on GPUs.
IISWC
Ren-Shuo Liu, Yun-Cheng Tsai, Chia-Lin Yang
2009 J jnl
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.
J. Signal Process. Syst.
Sung-Wen Wang, Shu-Sian Yang, Hong-Ming Chen, Chia-Lin Yang, Ja-Ling Wu
2009 J jnl
A Predictive Shutdown Technique for GPU Shader Processors.
IEEE Comput. Archit. Lett.
Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng
2009 J jnl
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2009 J jnl
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design.
J. Syst. Archit.
Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang
2009 J jnl
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin
2009 A conf
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems.
ISLPED
Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
2009 J jnl
T-trees: A tree-based representation for temporal and three-dimensional floorplanning.
ACM Trans. Design Autom. Electr. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2009 A conf
Thermal modeling for 3D-ICs with integrated microchannel cooling.
ICCAD
Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu
2008 A* conf
A progressive-ILP based routing algorithm for cross-referencing biochips.
DAC
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2008 J jnl
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2008 J jnl
Energy-Aware Flash Memory Management in Virtual Memory System.
IEEE Trans. Very Large Scale Integr. Syst.
Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
2008 J jnl
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
2007 A conf
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
ICME
Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen
2007 Misc conf
An architectural co-synthesis algorithm for energy-aware network-on-chip design.
SAC
Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su
2007 A conf
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
ICCAD
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 Misc conf
Cache leakage control mechanism for hard real-time systems.
CASES
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen
2007 — conf
Efficient obstacle-avoiding rectilinear steiner tree construction.
ISPD
Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
2007 A conf
Energy-efficient real-time task scheduling with task rejection.
DATE
Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King
2007 J jnl
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.
ACM J. Emerg. Technol. Comput. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 A conf
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.
ISLPED
Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 J jnl
Temporal floorplanning using the three-dimensional transitive closure subGraph.
ACM Trans. Design Autom. Electr. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2006 C conf
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation.
ISORC
Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang
2006 A conf
An energy-efficient virtual memory system with flash memory as the secondary storage.
ISLPED
Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang
2006 — conf
Branch Behavior Characterization for Multimedia Applications.
Asia-Pacific Computer Systems Architecture Conference
Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen
2006 A conf
Hierarchical value cache encoding for off-chip data bus.
ISLPED
Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
2006 A* conf
Placement of digital microfluidic biochips using the t-tree formulation.
DAC
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2005 — conf
Cache Leakage Management for Multi-programming Workloads.
Asia-Pacific Computer Systems Architecture Conference
Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung
2005 A conf
Joint exploration of architectural and physical design spaces with thermal consideration.
ISLPED
Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
2005 B conf
Reconfigurable Platform for Content Science Research.
RTCSA
Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen
2005 J jnl
Software-Controlled Cache Architecture for Energy Efficiency.
IEEE Trans. Circuits Syst. Video Technol.
Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu
2004 Misc conf
Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism.
CODES+ISSS
Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang
2004 A conf
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.
ISLPED
Chia-Lin Yang, Chien-Hao Lee
2004 B conf
Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations.
ECRTS
Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo
2004 Misc conf
Profit-driven uniprocessor scheduling with energy and timing constraints.
SAC
Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang
2004 — conf
Temporal floorplanning using 3D-subTCG.
ASP-DAC
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen
2004 A conf
Temporal floorplanning using the T-tree formulation.
ICCAD
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2004 J jnl
Tolerating memory latency through push prefetching for pointer-intensive applications.
ACM Trans. Archit. Code Optim.
Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee
2004 A conf
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.
DATE
Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
2004 — conf
Workload Characterization of the H.264/AVC Decoder.
PCM (2)
Tse-Tsung Shih, Chia-Lin Yang, Yi-Shin Tung
2004 J jnl
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
2003 A conf
A power-aware SWDR cell for reducing cache write power.
ISLPED
Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
2002 — conf
A Programmable Memory Hierarchy for Prefetching Linked Data Structures.
ISHPC
Chia-Lin Yang, Alvin R. Lebeck
2002 — conf
Using Intel Streaming SIMD Extensions for 3D Geometry Processing.
IEEE Pacific Rim Conference on Multimedia
Wan-Chun Ma, Chia-Lin Yang
2000 J jnl
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.
IEEE Trans. Computers
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
2000 A conf
Push vs. pull: data movement for linked data structures.
ICS
Chia-Lin Yang, Alvin R. Lebeck
1999 — conf
Annotated Memory References: A Mechanism for Informed Cache Management.
Euro-Par
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi
1998 A* conf
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.
MICRO
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck