Chia-Hsiang Yang

115 papers B 4C 3Misc 2Journal 55Unranked 51
YearRankTypeTitle / Venue / Authors
2026 — conf
A 144mW 161Mpixels/s Tensor Display Processor for 3D Virtual Reality.
ISSCC
Ching-Yen Lee, Yueh-Feng Tsai, Ying-Sheng Lin, Chia-Hsiang Yang
2026 J jnl
A 4.8-mW Hybrid Crypto SoC With Post-Quantum Cryptography and Lightweight Cryptography for Secure Neural Interfacing.
IEEE J. Solid State Circuits
Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang
2026 J jnl
A 40-nm 209-TOPS/W Reinforcement Learning Processor With Full Speculation Exploitation and Inference-Training Parallel Processing.
IEEE J. Solid State Circuits
Shih-Hao Chen, Ping-Sheng Wu, Brian Dean Soon, Chao-Hung Chen, Chih-Wei Liu, Chun-Lung Hsu, Chia-Hsiang Yang
2026 J jnl
A 40-nm 26.4 mW, 18.6 MS/s Image Reconstruction Processor for IoT Compressive Sensing.
IEEE J. Solid State Circuits
Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang
2026 J jnl
Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Hyo Gyuem Rhew, Heein Yoon, Chia-Hsiang Yang, Utsav Banerjee, Xueqing Li
2025 — conf
15.1 A 3.9mW 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface.
ISSCC
Tun-Yu Chang, Jeng-Bang Wang, Yu-Hsuan Tsai, Chia-Hsiang Yang
2025 — conf
17.3 A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation.
ISSCC
Liang-Hsin Lin, Yao-Kai Yang, Chia-Hsiang Yang
2025 — conf
2.8: A 210fps Image Signal Processor for 4K Ultra HD True Video Super Resolution.
ISSCC
Ying-Sheng Lin, Jun Nishimura, Chia-Hsiang Yang
2025 — conf
A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing.
CICC
Shih-Hao Chen, Ping-Sheng Wu, Brian Dean Soon, Chao-Hung Chen, Chun-Lung Hsu, Chih-Wei Liu, Chia-Hsiang Yang
2025 J jnl
A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots.
IEEE J. Solid State Circuits
I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
2025 J jnl
A 28nm Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.
IEEE Trans. Biomed. Circuits Syst.
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2025 J jnl
A 40-nm 131-mW 6.4-Gb/s 256 × 32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems.
IEEE J. Solid State Circuits
Tang Lee, Ting-Yang Chen, I-Hsuan Liu, Chia-Hsiang Yang
2025 J jnl
A 40-nm 169mW Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices.
IEEE Trans. Biomed. Circuits Syst.
Yi-Lin Lo, Yu-Chen Lo, Chia-Hsiang Yang
2025 J jnl
A 40-nm 3.9mW, 200words/Min Neural Signal Processor in Speech Decoding for Brain-Machine Interface.
IEEE Trans. Biomed. Circuits Syst.
Tun-Yu Chang, Jeng-Bang Wang, Yu-Hsuan Tsai, Yu Tsao, Chia-Hsiang Yang
2025 J jnl
A 44.3-mW 62.4-fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing.
IEEE J. Solid State Circuits
Yu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang
2025 J jnl
Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Wei-Zen Chen, Benton H. Calhoun, Chia-Hsiang Yang, Shreyas Sen, Jun Yang
2024 — conf
2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems.
ISSCC
Tang Lee, Ting-Yang Chen, I-Hsuan Liu, Chia-Hsiang Yang
2024 — conf
30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization.
ISSCC
Yi-Chen Chu, Yu-Cheng Lin, Yu-Chen Lo, Chia-Hsiang Yang
2024 — conf
A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices.
VLSI Technology and Circuits
Chun-Wei Chang, I-Ting Lin, Chia-Hsiang Yang
2024 J jnl
A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality.
IEEE J. Solid State Circuits
Wen-Cong Huang, I-Ting Lin, Ying-Sheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
2024 J jnl
A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices.
IEEE J. Solid State Circuits
Yu-Hsuan Tsai, Yi-Cheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Shi-Hao Chen, Chi-Shi Chen, Chia-Hsiang Yang
2024 — conf
A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks.
A-SSCC
I-Hsuan Liu, I-Ting Lin, Yueh-Feng Tsai, Jeng-Sheng Hsieh, Vincent Chen, Chuei-Tang Wang, Chia-Hsiang Yang, Douglas C. H. Yu
2024 J jnl
A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring.
IEEE J. Solid State Circuits
Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang
2024 J jnl
A 73.8k-Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition.
IEEE J. Solid State Circuits
Tzu-Wei Tong, Tai-Jung Chen, Yi-Yen Hsieh, Chia-Hsiang Yang
2024 — conf
A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-Based Speculation.
VLSI Technology and Circuits
Ping-Sheng Wu, Yu-Cheng Lin, Chia-Hsiang Yang
2024 J jnl
A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Yu-Cheng Lin, Ren-Hao Chiou, Chia-Hsiang Yang
2024 — conf
An 8.1-to-353 TOPS/W Energy-Aware Deep-Learning Accelerator Supporting Dynamic Neural Networks.
A-SSCC
Ting-Yang Chen, Yi-Lin Lo, Tun-Yu Chang, Chia-Hsiang Yang
2023 — conf
A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices.
VLSI Technology and Circuits
Yi-Lin Lo, Yu-Chen Lo, Chia-Hsiang Yang
2023 — conf
A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing.
VLSI Technology and Circuits
Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang
2023 — conf
A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow.
ISSCC
Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
2023 — conf
A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots.
ISSCC
I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
2023 — conf
A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing.
VLSI Technology and Circuits
Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang
2023 J jnl
A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator.
IEEE J. Solid State Circuits
Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang
2023 — conf
A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition.
A-SSCC
Tzu-Wei Tong, Yi-Yen Hsieh, Tai-Jung Chen, Chia-Hsiang Yang
2023 J jnl
A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction.
IEEE J. Solid State Circuits
Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang
2023 — conf
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.
ISSCC
Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2023 J jnl
An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices.
IEEE J. Solid State Circuits
Sheng-Jung Yu, Yu-Chi Lee, Liang-Hsin Lin, Chia-Hsiang Yang
2023 J jnl
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping.
IEEE Trans. Biomed. Circuits Syst.
Chung-Hsuan Yang, Yi-Chung Wu, Yen-Lung Chen, Chao-Hsi Lee, Jui-Hung Hung, Chia-Hsiang Yang
2022 — conf
A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality.
VLSI Technology and Circuits
Wen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
2022 — conf
A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training.
VLSI Technology and Circuits
Zih-Sing Fu, Yu-Chi Lee, Alex Park, Chia-Hsiang Yang
2022 — conf
A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing.
VLSI Technology and Circuits
Yu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang
2022 — conf
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction.
ISSCC
Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang
2022 J jnl
Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal.
IEEE J. Biomed. Health Informatics
Ying-Sheng Lin, Yi-Pao Wu, Yi-Chung Wu, Pei-Lin Lee, Chia-Hsiang Yang
2022 — conf
Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression.
MWSCAS
Chen-Chien Kao, Yi-Yen Hsieh, Chao-Hung Chen, Chia-Hsiang Yang
2022 J jnl
Hybrid Precoding Baseband Processor for 64 × 64 Millimeter Wave MIMO Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chen-Chien Kao, Chiao-En Chen, Chia-Hsiang Yang
2021 — conf
4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images.
ISSCC
Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang
2021 — conf
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices.
A-SSCC
Sheng-Jung Yu, Yu-Chi Lee, Chia-Hsiang Yang
2021 J jnl
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots.
IEEE J. Solid State Circuits
Chieh Chung, Chia-Hsiang Yang
2021 — conf
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring.
A-SSCC
Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang
2021 J jnl
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.
IEEE J. Solid State Circuits
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2021 Misc conf
A Color Doppler Processing Engine with an Adaptive Clutter Filter for Portable Ultrasound Imaging Devices.
ICASSP
Yi-Lin Lo, Chia-Hsiang Yang
2021 J jnl
A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome.
IEEE Trans. Parallel Distributed Syst.
Yen-Lung Chen, Bo-Yi Chang, Chia-Hsiang Yang, Tzi-Dar Chiueh
2021 J jnl
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification.
IEEE J. Solid State Circuits
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2021 — conf
Design optimization for ADMM-Based SVM Training Processor for Edge Computing.
AICAS
Shuo-An Huang, Yi-Yen Hsieh, Chia-Hsiang Yang
2020 — conf
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.
ISSCC
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2020 — conf
21.2 A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots.
ISSCC
Chieh Chung, Chia-Hsiang Yang
2020 J jnl
A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement.
IEEE Trans. Circuits Syst.
Yung-Jen Lin, Yu-Chi Lee, Hao-Min Liu, Herming Chiueh, Tai-Shih Chi, Chia-Hsiang Yang
2020 J jnl
A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control.
IEEE J. Solid State Circuits
Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang
2020 — conf
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems.
VLSI Circuits
Chi-Chih Wen, Yu-Chi Lee, Yi-Chung Wu, Chen-Chien Kao, Chia-Hsiang Yang
2020 J jnl
A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices.
IEEE J. Solid State Circuits
Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang
2020 C conf
A CycleGAN Accelerator for Unsupervised Learning on Mobile Devices.
ISCAS
Yi-Yen Hsieh, Yu-Chi Lee, Chia-Hsiang Yang
2020 — conf
AI Acceleration with RISC-V for Edge Computing.
VLSI-DAT
Chia-Hsiang Yang
2020 — conf
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition.
A-SSCC
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2020 B conf
Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax.
GLOBECOM
Yao-Pin Wang, Chi-Chih Wen, Chen-Chien Kao, Chung-Jung Huang, Der-Zheng Liu, Chia-Hsiang Yang
2020 — conf
Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS.
VLSI-DAT
Herming Chiueh, Chia-Hsiang Yang, Charles H.-P. Wen, Chao-Guang Yang, Po-Hao Chien, Ching-Yang Hung, Yu-Jui Chen, Yao-Pin Wang, Chin-Fong Chiu, Jer Lin
2019 J jnl
A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals.
IEEE J. Solid State Circuits
Yu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang
2019 — conf
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices.
AICAS
Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang
2019 — conf
A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training.
A-SSCC
Cheng-Hsun Lu, Yi-Chung Wu, Chia-Hsiang Yang
2019 J jnl
A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing.
CoRR
Shuo-An Huang, Chia-Hsiang Yang
2019 J jnl
An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yan-Tong Chen, Wei-Cheng Sun, Chung-Chao Cheng, Tsung-Lin Tsai, Yeong-Luh Ueng, Chia-Hsiang Yang
2019 J jnl
An LDPC-Coded SCMA Receiver With Multi-User Iterative Detection and Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Cheng Sun, Yu-Chieh Su, Yeong-Luh Ueng, Chia-Hsiang Yang
2019 J jnl
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem.
IEEE Trans. Biomed. Eng.
Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2019 J jnl
Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems.
IEEE Trans. Signal Process.
Wei-Cheng Sun, Yan-Tong Chen, Chia-Hsiang Yang, Yeong-Luh Ueng
2019 — conf
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs.
VLSI-DAT
Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang
2018 J jnl
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip.
IEEE Trans. Circuits Syst. II Express Briefs
Ting-I Chou, Kwuang-Han Chang, Jia-Yin Jhang, Shih-Wen Chiu, Guoxing Wang, Chia-Hsiang Yang, Herming Chiueh, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang
2018 — conf
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control.
VLSI Circuits
Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang
2018 — conf
A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals.
VLSI Circuits
Yu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang
2018 C conf
A 2×2-16×16 Reconfigurable GGMD Processor for MIMO Communication Systems.
ISCAS
Chih-Hsuan Chiang, Shuo-An Huang, Chiao-En Chen, Chia-Hsiang Yang
2018 J jnl
A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chun-Yu Yeh, Ting-Chung Chu, Chiao-En Chen, Chia-Hsiang Yang
2018 J jnl
Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits
Tsung-Hsien Lin, Chia-Hsiang Yang, Seung-Tak Ryu
2018 — conf
Massive MIMO detection VLSI design.
VLSI-DAT
Chia-Hsiang Yang
2017 — conf
14.8 A 135mW fully integrated data processor for next-generation sequencing.
ISSCC
Yi-Chung Wu, Jui-Hung Hung, Chia-Hsiang Yang
2017 J jnl
A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing.
IEEE Trans. Biomed. Circuits Syst.
Yi-Chung Wu, Chia-Hua Chang, Jui-Hung Hung, Chia-Hsiang Yang
2017 J jnl
A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits
Mao-Ruei Li, Chia-Hsiang Yang, Yeong-Luh Ueng
2017 J jnl
A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu-Cheng Tsai, Chiao-En Chen, Chia-Hsiang Yang
2017 — conf
An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors.
VTC Spring
Wei-Cheng Sun, Chia-Hsiang Yang, Yen-Ming Chen, Yeong-Luh Ueng
2017 C conf
Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables.
ISCAS
Hsin-Tzu Lin, Yi-Chung Wu, Ping-Hsuan Hsieh, Chia-Hsiang Yang
2016 J jnl
A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving.
IEEE Trans. Circuits Syst. I Regul. Pap.
Cheng-Yen Lee, Ping-Hsuan Hsieh, Chia-Hsiang Yang
2016 — conf
Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease.
BioCAS
Ting-I Chou, Shih-Wen Chiu, Kwuang-Han Chang, Yi-Ju Chen, Chen-Ting Tang, Chung-Hung Shih, Chih-Cheng Hsieh, Meng-Fan Chang, Chia-Hsiang Yang, Herming Chiueh, Kea-Tiong Tang
2016 Misc conf
Error-resilient sequential cells with successive time borrowing for stochastic computing.
ICASSP
Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou
2016 J jnl
sBWT: memory efficient implementation of the hardware-acceleration-friendly Schindler transform for the fast biological sequence mapping.
Bioinform.
Chia-Hua Chang, Min-Te Chou, Yi-Chung Wu, Ting-Wei Hong, Yun-Lung Li, Chia-Hsiang Yang, Jui-Hung Hung
2015 — conf
A 794Mbps 135mW iterative detection and decoding receiver for 4×4 LDPC-coded MIMO systems in 40nm.
VLSIC
Wei-Hsuan Wu, Wei-Cheng Sun, Chia-Hsiang Yang, Yeong-Luh Ueng
2015 J jnl
A Systolic Array Based GTD Processor With a Parallel Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chia-Hsiang Yang, Chun-Wei Chou, Chia-Shen Hsu, Chiao-En Chen
2015 J jnl
An 81.6 µW FastICA Processor for Epileptic Seizure Detection.
IEEE Trans. Biomed. Circuits Syst.
Chia-Hsiang Yang, Yi-Hsin Shih, Herming Chiueh
2015 J jnl
An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Cheng Sun, Wei-Hsuan Wu, Chia-Hsiang Yang, Yeong-Luh Ueng
2015 J jnl
An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems.
IEEE Trans. Wirel. Commun.
Chiao-En Chen, Yu-Cheng Tsai, Chia-Hsiang Yang
2014 — conf
24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia.
ISSCC
Kea-Tiong Tang, Shih-Wen Chiu, Chung-Hung Shih, Chia-Ling Chang, Chia-Min Yang, Da-Jeng Yao, Jen-Huo Wang, Chien-Ming Huang, Hsin Chen, Kwuang-Han Chang, Chih-Cheng Hsieh, Ting-Hau Chang, Meng-Fan Chang, Chia-Min Wang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu
2014 J jnl
A 5.4 µW Soft-Decision BCH Decoder for Wireless Body Area Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chia-Hsiang Yang, Ting-Ying Huang, Mao-Ruei Li, Yeong-Luh Ueng
2014 J jnl
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control.
IEEE J. Solid State Circuits
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu
2014 J jnl
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia.
IEEE Trans. Biomed. Circuits Syst.
Shih-Wen Chiu, Jen-Huo Wang, Kwuang-Han Chang, Ting-Hau Chang, Chia-Min Wang, Chia-Lin Chang, Chen-Ting Tang, Chien-Fu Chen, Chung-Hung Shih, Han-Wen Kuo, Li-Chun Wang, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu, Kea-Tiong Tang
2014 J jnl
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Chao Cheng, Jeng-Da Yang, Huang-Chang Lee, Chia-Hsiang Yang, Yeong-Luh Ueng
2013 — conf
A 191μW BPSK demodulator for data and power telemetry in biomedical implants.
ACM Great Lakes Symposium on VLSI
Li-Lan Wang, Chia-Hsiang Yang, Herming Chiueh
2013 — conf
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control.
ISSCC
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu
2013 J jnl
An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems.
CoRR
Chiao-En Chen, Chia-Hsiang Yang
2013 — conf
Power and area reduction in multi-stage addition using operand segmentation.
VLSI-DAT
Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou
2012 J jnl
A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios.
IEEE J. Solid State Circuits
Tsung-Han Yu, Chia-Hsiang Yang, Danijela Cabric, Dejan Markovic
2012 — conf
Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection.
APSIPA
Yi-Hsin Shih, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh
2012 J jnl
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example.
IEEE J. Solid State Circuits
Chia-Hsiang Yang, Tsung-Han Yu, Dejan Markovic
2011 B conf
A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection.
GLOBECOM
Fang-Li Yuan, Chia-Hsiang Yang, Dejan Markovic
2011 B conf
An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing.
GLOBECOM
Tsung-Han Yu, Chia-Hsiang Yang, Dejan Markovic, Danijela Cabric
2009 — conf
A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS.
ESSCIRC
Chia-Hsiang Yang, Dejan Markovic
2009 J jnl
A Flexible DSP Architecture for MIMO Sphere Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chia-Hsiang Yang, Dejan Markovic
2008 — conf
A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels.
ICC
Chia-Hsiang Yang, Dejan Markovic
2008 B conf
A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications.
GLOBECOM
Chia-Hsiang Yang, Dejan Markovic
2004 — conf
Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems.
ISCAS (4)
Chia-Hsiang Yang, Yu-Hsuan Lin, Shih-Chun Lin, Tzi-Dar Chiueh