Chia-Chun Tsai

55 papers B 3C 6Misc 3Journal 25Unranked 18
YearRankTypeTitle / Venue / Authors
2022 J jnl
A surface defect detection system for golden diamond pineapple based on CycleGAN and YOLOv4.
J. King Saud Univ. Comput. Inf. Sci.
Ssu-Han Chen, Yu-Wei Lai, Chung-Lun Kuo, Chieh-Yi Lo, Yu-Sung Lin, Yan-Rung Lin, Chih-Hsiang Kang, Chia-Chun Tsai
2021 J jnl
SMD LED chips defect detection using a YOLOv3-dense model.
Adv. Eng. Informatics
Ssu-Han Chen, Chia-Chun Tsai
2020 — conf
3D Hand Gesture Recognition for Drone Control in Unity
CASE
Chia-Chun Tsai, Chih-Chia Kuo, Yen-Lun Chen
2019 — conf
Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period.
ISOCC
Chia-Chun Tsai
2018 — conf
Embedded bus switches on 3D data bus for critical access time reduction.
LASCAS
Chia-Chun Tsai
2017 — conf
Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters.
ISVLSI
Chia-Chun Tsai
2016 J jnl
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform.
IEEE Trans. Circuits Syst. II Express Briefs
Shin-Chi Lai, Wen-Ho Juang, Yueh-Shu Lee, Shin-Hao Chen, Ke-Horng Chen, Chia-Chun Tsai, Chiung-Hon Lee
2015 B conf
Improved PSO based home energy management systems integrated with demand response in a smart grid.
CEC
Hong-Tzer Yang, Chiao-Tung Yang, Chia-Chun Tsai, Guan-Jhih Chen, Szu-Yao Chen
2013 Misc conf
A reduced Li-Ion battery charger for portable applications.
ICNC
Chia-Chun Tsai
2013 Misc conf
Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology.
CISIS
Trong-Yen Lee, Min-Jea Liu, Chia-Chen Fan, Chia-Chun Tsai, Haixia Wu
2012 J jnl
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.
Integr.
Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee
2012 J jnl
Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs.
ACM Trans. Design Autom. Electr. Syst.
Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai
2012 — conf
Micro fuel cell power management circuit design for portable devices.
FSKD
Chia-Chun Tsai, Tsung-Ming Liu, Trong-Yen Lee
2011 J jnl
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration.
Integr.
Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee
2011 J jnl
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
2011 J jnl
The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B.
J. Circuits Syst. Comput.
Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee
2010 — conf
Antenna Violation Avoidance/Fixing for X-clock routing.
ISQED
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
2010 C conf
Double-via insertion enhanced X-architecture clock routing for reliability.
ISCAS
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
2010 J jnl
Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems.
J. Inf. Sci. Eng.
Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai
2009 J jnl
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters.
J. Circuits Syst. Comput.
Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee
2009 J jnl
Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion.
Circuits Syst. Signal Process.
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
2009 J jnl
The Design of a Li-ion Battery Charger Based on Multimode LDO Technology.
J. Circuits Syst. Comput.
Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee
2008 J jnl
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
2008 C conf
Layer assignment considering manufacturability in X-architecture clock tree.
CIT
Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee
2008 — conf
X-clock routing based on pattern matching.
SoCC
Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
2007 — conf
An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems.
IMECS
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
2007 — conf
Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems.
IIH-MSP
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
2007 J jnl
Zero-Skew Driven Buffered RLC Clock Tree Construction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
2006 C conf
A single chip image sensor embedded smooth spatial filter with A/D conversion.
ISCAS
Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao
2006 C conf
Coupling aware RLC-based clock routings for crosstalk minimization.
ISCAS
Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao
2006 C conf
Inductance extraction for general interconnect structures.
ISCAS
Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai
2006 — conf
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.
APCCAS
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
2006 — conf
Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion.
ICICIC (2)
Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai
2006 — conf
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.
APCCAS
Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee
2006 J jnl
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design.
J. Inf. Sci. Eng.
Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu
2005 — conf
A new CCII-based pipelined analog to digital converter.
ISCAS (6)
Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen
2005 — conf
A new low-power turbo decoder using HDA-DHDD stopping iteration.
ISCAS (2)
Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang
2005 — conf
Zero-Skew Driven for RLC Clock Tree Construction in SoC.
ICITA (1)
Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee
2004 J jnl
An embedded analog spatial filter design of the current-mode CMOS image sensor.
IEEE Trans. Consumer Electron.
Pei-Yung Hsiao, Yu-Chun Hsu, Wen-Ta Lee, Chia-Chun Tsai, Chia-Hao Lee
2004 B conf
RCGES: Retargetable Code Generation for Embedded Systems.
ATVA
Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang
2000 J jnl
Efficient routability check algorithms for segmented channel routing.
ACM Trans. Design Autom. Electr. Syst.
Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai
1999 — conf
An Automatic Router for the Pin Grid Array Package.
ASP-DAC
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
1999 — conf
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits.
ASP-DAC
Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho
1999 C conf
An Even Wiring Approach to the Ball Grid Array Package Routing.
ICCD
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
1998 J jnl
NEWS: a net-even-wiring system for the routing on a multilayer PGA package.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen
1997 J jnl
Hmap: a fast mapper for EPGAs using extended GBDD hash tables.
ACM Trans. Design Autom. Electr. Syst.
Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen
1996 J jnl
Performance driven bus buffer insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng
1995 — conf
Performance driven multiple-source bus synthesis using buffer insertion.
ASP-DAC
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
1994 J jnl
A Linear Time Algorithm for Planar Moat Routing.
J. Inf. Sci. Eng.
Chia-Chun Tsai, Sao-Jie Chen
1992 J jnl
An H-V alternating router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
1992 Misc conf
Minimum Partition for the Space Region of VLSI Layout.
VLSI Design
Pei-Yung Hsiao, Chiao-Yi Lin, Chia-Chun Tsai
1991 J jnl
A knowledge-based program for compacting mask layout of integrated circuits.
Comput. Aided Des.
Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng
1990 B conf
A new plane-sweep algorithm based on spatial data structure for overlapped rectangles in 2-D plane.
COMPSAC
Pei-Yung Hsiao, Chia-Chun Tsai
1990 J jnl
An
J. Inf. Sci. Eng.
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
1990 J jnl
Generalized terminal connectivity problem for multilayer layout scheme.
Comput. Aided Des.
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng