Chia-Chih Yen

12 papers A 1Misc 1Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2020 A conf
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification.
DATE
Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang
2012 — conf
A formal method to improve SystemVerilog functional coverage.
HLDVT
An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou
2010 J jnl
FSM-Based Formal Compliance Verification of Interface Protocols.
J. Inf. Sci. Eng.
Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou
2008 Misc conf
A General Failure Candidate Ranking Framework for Silicon Debug.
VTS
Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu
2006 J jnl
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.
IEEE Trans. Computers
Chia-Chih Yen, Jing-Yang Jou
2006 — conf
Diagnosing Silicon Failures Based on Functional Test Patterns.
MTV
Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu
2005 — conf
An optimum algorithm for compacting error traces for efficient functional debugging.
HLDVT
Chia-Chih Yen, Jing-Yang Jou
2004 J jnl
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation.
IEEE Des. Test Comput.
Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
2004 — conf
Enhancing sequential depth computation with a branch-and-bound algorithm.
HLDVT
Chia-Chih Yen, Jing-Yang Jou
2004 — conf
On compliance test of on-chip bus for SOC.
ASP-DAC
Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou
2002 — conf
A Practical Approach to Cycle Bound Estimation for Property Checking.
IWLS
Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
2001 — conf
Automatic Functional Vector Generation Using the Interacting FSM Model.
ISQED
Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou