Chi-Ying Tsui - RankMe

283 papers A* 12A 20B 10C 48Misc 5Journal 102Unranked 84

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding. ISSCC Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Di Pang, Songchen Ma, Xijie Huang, Shih-Yang Liu, Dong Zhang, Zhichao Lu, Luhong Liang, Chi-Ying Tsui, Fengbin Tu, Liang Zhao, Kwang-Ting Cheng
2026	—	`conf`	36.6 A Sparsity-Aware Neural Interface with CIM-Based Predictive Focused Sampling for Hotspot Spike Tracking. ISSCC Hui Wu, Fengshi Tian, Jinbo Chen, Zhipeng Liao, Hongyong Zhang, Xing Liu, Wenjun Zou, Sirui Cheng, Zhao Zhang, Jianlong Xu, Chi-Ying Tsui, Kwang-Ting Tim Cheng, Jie Yang, Mohamad Sawan
2026	J	`jnl`	Balancing FP8 Computation Accuracy and Efficiency on Digital CIM via Shift-Aware On-the-fly Aligned-Mantissa Bitwidth Prediction. CoRR Liang Zhao, Kunming Shao, Zhipeng Liao, Xijie Huang, Tim Kwang-Ting Cheng, Chi-Ying Tsui, Yi Zou
2026	J	`jnl`	Configurable Dataflow and Adaptive Mapping Optimization for Hybrid ReRAM and SRAM Compute-in-Memory Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jingyu He, Xiaomeng Wang, Kunming Shao, Kwang-Ting Cheng, Chi-Ying Tsui
2026	J	`jnl`	DS-CIM: Digital Stochastic Computing-In-Memory Featuring Accurate OR-Accumulation via Sample Region Remapping for Edge AI Models. CoRR Kunming Shao, Liang Zhao, Jiangnan Yu, Zhipeng Liao, Xiaomeng Wang, Yi Zou, Tim Kwang-Ting Cheng, Chi-Ying Tsui
2026	—	`conf`	Exploiting the Irregular Input Sparsity in Systolic Array-based DNN Accelerators via Local Soft Pooling. ASP-DAC Desheng Fu, Jingbo Jiang, Xiaomeng Wang, Jingyang Zhu, Xizi Chen, Chi-Ying Tsui
2025	—	`conf`	A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation. ISSCC Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Luhong Liang, Yitong Zhou, Di Pang, Manto Yung, Dong Zhang, Xijie Huang, Shih-Yang Liu, Yongkun Wu, Fengshi Tian, Chi-Ying Tsui, Fengbin Tu, Kwang-Ting Cheng
2025	C	`conf`	A Dual-Mode One-stage R ISCAS Tsz Fai Kwok, Yuan Yao, Pok Man Leung, Wing-Hung Ki, Chi-Ying Tsui
2025	C	`conf`	A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination. ISCAS Liang Zhao, Kunming Shao, Fengshi Tian, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui, Yi Zou
2025	J	`jnl`	A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination. CoRR Liang Zhao, Kunming Shao, Fengshi Tian, Kwang-Ting Cheng, Chi-Ying Tsui, Yi Zou
2025	J	`jnl`	A Memory-Efficient Retrieval Architecture for RAG-Enabled Wearable Medical LLMs-Agents. CoRR Zhipeng Liao, Kunming Shao, Jiangnan Yu, Liang Zhao, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui, Jie Yang, Mohamad Sawan
2025	C	`conf`	Analysis and Prevention of Coupling-Dependent Data Flipping in Series-Series Resonant Wireless Power Transfer Systems. ISCAS Yuan Yao, Sayan Sarkar, Fengshi Tian, Wing-Hung Ki, Chi-Ying Tsui, Yang Liu
2025	J	`jnl`	BioPI: An Energy Efficient and Low-Latency Neuromorphic Pipelined System With Joint Design Optimizations of Sensor-Algorithm-Processor for Wearable Healthcare. IEEE Trans. Circuits Syst. Artif. Intell. Fengshi Tian, Jinbo Chen, Jiakun Zheng, Hui Wu, Jingyu He, Xiaomeng Wang, Chaoming Fang, Yuan Yao, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting Cheng
2025	A	`conf`	DIRC-RAG: Accelerating Edge RAG with Robust High-Density and High-Loading-Bandwidth Digital In-ReRAM Computation. ISLPED Kunming Shao, Zhipeng Liao, Jiangnan Yu, Liang Zhao, Qiwei Li, Xijie Huang, Jingyu He, Fengshi Tian, Yi Zou, Xiaomeng Wang, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2025	J	`jnl`	DIRC-RAG: Accelerating Edge RAG with Robust High-Density and High-Loading-Bandwidth Digital In-ReRAM Computation. CoRR Kunming Shao, Zhipeng Liao, Jiangnan Yu, Liang Zhao, Qiwei Li, Xijie Huang, Jingyu He, Fengshi Tian, Yi Zou, Xiaomeng Wang, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2025	C	`conf`	DPE-CIM: Compute-In-Memory Accelerator using Dynamic Posit Encoding and Speculative Alignment. ISCAS Jingyu He, Kwang-Ting Cheng, Chi-Ying Tsui
2025	—	`conf`	E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables. CICC Fengshi Tian, Jinbo Chen, Kunming Shao, Zilu Liu, Jiakun Zheng, Hui Wu, Chaoming Fang, Xiaomeng Wang, Ziyang Shen, Pingcheng Dong, Yuan Yao, Xuliang Wang, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting Cheng
2025	J	`jnl`	Exploiting the Memory-Compute-Coupling Feature for CIM Accelerator Design Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yongkun Wu, Xiaomeng Wang, Jia Chen, Zhenhua Zhu, Jingyu He, Pingcheng Dong, Yonghao Tan, Xin Zhao, Liang Chang, Yu Wang, Fengbin Tu, Chi-Ying Tsui, Kwang-Ting Cheng
2025	B	`conf`	FAS-RIS-Aided Multi-User Systems With Linear Precoding: Random Matrix Analysis and Two-Timescale Design. GLOBECOM Xin Zhang, Dongfang Xu, Jingjing Wang, Shenghui Song, Chi-Ying Tsui, Derrick Wing Kwan Ng, Mérouane Debbah
2025	J	`jnl`	FedLAM: Low-latency Wireless Federated Learning via Layer-wise Adaptive Modulation. CoRR Linping Qu, Shenghui Song, Chi-Ying Tsui
2025	J	`jnl`	High Efficiency Active Rectifier Using SAR Digital-to-Time Converter for Wireless Power Transfer System. IEEE Trans. Circuits Syst. I Regul. Pap. Yang Liu, Chenchang Zhan, Chi-Ying Tsui, Wing-Hung Ki
2025	J	`jnl`	Hysteresis-Dependent Synchronized Load Shift Keying and Reconfigurable Class-D Power Amplifier-Based Fully Integrated Adaptive Control in Wireless Power Transfer System. IEEE Trans. Circuits Syst. I Regul. Pap. Sayan Sarkar, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui
2025	J	`jnl`	Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding. IEEE Trans. Very Large Scale Integr. Syst. Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross
2025	B	`conf`	LDPC Code Optimisation for OTFS Modulation with MP Detection. GLOBECOM Chong Zhang, Shenghui Song, Chi-Ying Tsui, Jinhong Yuan
2025	C	`conf`	NeuroEye: A 54.59mW, 12200FPS Event-Driven Near-Sensor Eye-Tracking Processor with Pipelined Spatial-Temporal Spike-Streaming. ISCAS Jiakun Zheng, Fengshi Tian, Jinbo Chen, Chaoming Fang, Yuan Yao, Jie Yang, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2025	A	`conf`	SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. DATE Kunming Shao, Fengshi Tian, Xiaomeng Wang, Jiakun Zheng, Jia Chen, Jingyu He, Hui Wu, Jinbo Chen, Xihao Guan, Yi Deng, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2024	J	`jnl`	A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices. IEEE J. Solid State Circuits Xiaodong Meng, Xing Li, Chi-Ying Tsui, Wing-Hung Ki, Weiqiang Liu
2024	A	`conf`	AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit. DATE Jingyu He, Fengbin Tu, Kwang-Ting Cheng, Chi-Ying Tsui
2024	C	`conf`	Adaptive Digitally-Controlled Active Rectifier-Based Receiver for Bioimplants. ISCAS Sayan Sarkar, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui
2024	J	`jnl`	Analysis of Off-Resonant Flexible Tertiary Coils in Biomedical Implants for Back Telemetry Detection. IEEE Trans. Circuits Syst. I Regul. Pap. Sayan Sarkar, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui
2024	C	`conf`	BOLS: A Bionic Sensor-direct On-chip Learning System with Direct-Feedback-Through-Time for Personalized Wearable Health Monitoring. ISCAS Fengshi Tian, Jiakun Zheng, Jingyu He, Jinbo Chen, Xiaomeng Wang, Chaoming Fang, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting Cheng
2024	—	`conf`	Design of a Fully Integrated Hysteretic Controlled Reconfigurable Transmitter for Bioimplants. EMBC Sayan Sarkar, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui
2024	J	`jnl`	Energy-Efficient Channel Decoding for Wireless Federated Learning: Convergence Analysis and Adaptive Design. CoRR Linping Qu, Yuyi Mao, Shenghui Song, Chi-Ying Tsui
2024	J	`jnl`	Energy-Efficient Channel Decoding for Wireless Federated Learning: Convergence Analysis and Adaptive Design. IEEE Trans. Wirel. Commun. Linping Qu, Yuyi Mao, Shenghui Song, Chi-Ying Tsui
2024	J	`jnl`	FedAQ: Communication-Efficient Federated Edge Learning via Joint Uplink and Downlink Adaptive Quantization. CoRR Linping Qu, Shenghui Song, Chi-Ying Tsui
2024	B	`conf`	How Robust is Federated Learning to Communication Error? A Comparison Study Between Uplink and Downlink Channels. WCNC Linping Qu, Shenghui Song, Chi-Ying Tsui, Yuyi Mao
2024	J	`jnl`	Partial Knowledge Distillation for Alleviating the Inherent Inter-Class Discrepancy in Federated Learning. CoRR Xiaoyu Gan, Xizi Chen, Jingyang Zhu, Xiaomeng Wang, Jingbo Jiang, Chi-Ying Tsui
2024	A*	`conf`	RWriC: A Dynamic Writing Scheme for Variation Compensation for RRAM-based In-Memory Computing. DAC Yucong Huang, Jingyu He, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui, Terry Tao Ye
2024	A	`conf`	ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM Cells. ICCAD Xiaomeng Wang, Jingyu He, Kunming Shao, Jiakun Zheng, Fengshi Tian, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2024	J	`jnl`	SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. CoRR Kunming Shao, Fengshi Tian, Xiaomeng Wang, Jiakun Zheng, Jia Chen, Jingyu He, Hui Wu, Jinbo Chen, Xihao Guan, Yi Deng, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2024	C	`conf`	Time Domain Analysis of Secondary Stage With Series Resonance Driving Rectifier Load. ISCAS Wing-Hung Ki, Yuan Yao, Chi-Ying Tsui
2024	—	`conf`	Time Domain Analysis of WPT System with Parallel Resonant Secondary Stage Driving Rectifier Load. APCCAS Wing-Hung Ki, Yuan Yao, Chi-Ying Tsui
2023	J	`jnl`	A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications. CoRR Xiaomeng Wang, Fengshi Tian, Xizi Chen, Jiakun Zheng, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting Cheng, Chi-Ying Tsui
2023	—	`conf`	A Primary Driver with Real-Time Resonance Tracking for Wireless-Powered Implantable Medical Devices. A-SSCC Xiaodong Meng, Xing Li, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki
2023	J	`jnl`	A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad. IEEE Trans. Circuits Syst. II Express Briefs Xianghong Hu, Xuejiao Liu, Yu Liu, Haowei Zhang, Xijie Huang, Xihao Guan, Luhong Liang, Chi-Ying Tsui, Xiaoming Xiong, Kwang-Ting Cheng
2023	C	`conf`	Accelerating Large Kernel Convolutions with Nested Winograd Transformation. VLSI-SoC Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2023	—	`conf`	Accelerating Large Kernel Convolutions with Nested Winograd Transformation. VLSI-SoC (Selected Papers) Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2023	A*	`conf`	AutoDCIM: An Automated Digital CIM Compiler. DAC Jia Chen, Fengbin Tu, Kunming Shao, Fengshi Tian, Xiao Huo, Chi-Ying Tsui, Kwang-Ting Cheng
2023	—	`conf`	BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare. ESSCIRC Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jiakun Zheng, Hui Wu, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng
2023	—	`conf`	Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System. AICAS Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng
2023	J	`jnl`	Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications. IEEE Access Soumitra Pal, Gajendranath Chowdary, Wing-Hung Ki, Chi-Ying Tsui
2023	J	`jnl`	How Robust is Federated Learning to Communication Error? A Comparison Study Between Uplink and Downlink Channels. CoRR Linping Qu, Shenghui Song, Chi-Ying Tsui, Yuyi Mao
2023	A*	`conf`	Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification. DAC Xizi Chen, Rui Pan, Xiaomeng Wang, Fengshi Tian, Chi-Ying Tsui
2023	—	`conf`	NOLS: A Near-sensor On-chip Learning System with Direct Feedback Alignment for Personalized Wearable Heart Health Monitoring. BioCAS Fengshi Tian, Shiqi Zhao, Jingyu He, Jinbo Chen, Xiaomeng Wang, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng
2023	—	`conf`	RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing. ASP-DAC Jingyu He, Yucong Huang, Miguel Angel Lastras-Montaño, Terry Tao Ye, Chi-Ying Tsui, Kwang-Ting Cheng
2023	—	`conf`	SNNOpt: An Application-Specific Design Framework for Spiking Neural Networks. AICAS Jingyu He, Ziyang Shen, Fengshi Tian, Jinbo Chen, Jie Yang, Mohamad Sawan, Hsiang-Ting Chen, Paul Bogdan, Chi-Ying Tsui
2023	—	`conf`	Step-GRAND: A Low Latency Universal Soft-Input Decoder. GLOBECOM (Workshops) Syed Mohsin Abbas, Chi-Ying Tsui, Marwan Jalaleddine, Warren J. Gross
2023	J	`jnl`	Step-GRAND: A Low Latency Universal Soft-input Decoder. CoRR Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross
2023	J	`jnl`	Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2022	C	`conf`	A 16-bit Encrypted On-chip Embedded System for Implantable Medical Devices. ISCAS Sayan Sarkar, Jingbo Jiang, Wing-Hung Ki, Chi-Ying Tsui
2022	C	`conf`	Design Strategy of Off-Resonant Tertiary Coils for Uplink Detection in Biomedical Implants. ISCAS Sayan Sarkar, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui
2022	B	`conf`	FedDQ: Communication-Efficient Federated Learning with Descending Quantization. GLOBECOM Linping Qu, Shenghui Song, Chi-Ying Tsui
2022	J	`jnl`	Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Soumitra Pal, Wing-Hung Ki, Chi-Ying Tsui
2022	—	`conf`	TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network. AICAS Xiaomeng Wang, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, Chi-Ying Tsui
2021	J	`jnl`	A Reconfigurable Winograd CNN Accelerator with Nesting Decomposition Algorithm for Computing Convolution with Large Filters. CoRR Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2021	J	`jnl`	FedDQ: Communication-Efficient Federated Learning with Descending Quantization. CoRR Linping Qu, Shenghui Song, Chi-Ying Tsui
2021	J	`jnl`	Microshift: An Efficient Image Compression Algorithm for Hardware. CoRR Bo Zhang, Pedro V. Sander, Chi-Ying Tsui, Amine Bermak
2021	J	`jnl`	Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation. CoRR Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2020	J	`jnl`	A 40.68-MHz Active Rectifier With Hybrid Adaptive On/Off Delay-Compensation Scheme for Biomedical Implantable Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Lin Cheng, Xinyuan Ge, Langyu Hu, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui
2020	J	`jnl`	A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique. IEEE J. Solid State Circuits Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu
2020	J	`jnl`	A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing. IEEE J. Solid State Circuits Xiaopeng Zhong, Man-Kay Law, Chi-Ying Tsui, Amine Bermak
2020	J	`jnl`	A Low-Power Motion Estimation Architecture for HEVC Based on a New Sum of Absolute Difference Computation. IEEE Trans. Circuits Syst. Video Technol. Luheng Jia, Chi-Ying Tsui, Oscar C. Au, Kebin Jia
2020	J	`jnl`	Construction of Multi-Kernel Polar Codes With Kernel Substitution. IEEE Wirel. Commun. Lett. ChenYang Xia, Chi-Ying Tsui, YouZhe Fan
2020	—	`conf`	Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications. ASP-DAC Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu
2020	A*	`conf`	Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation. DAC Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2019	J	`jnl`	A -12.3 dBm UHF Passive RFID Sense Tag for Grid Thermal Monitoring. IEEE Trans. Ind. Electron. Bo Wang, Man-Kay Law, Jun Yi, Chi-Ying Tsui, Amine Bermak
2019	—	`conf`	A 2.2μW 600kHz Frequency-Locked Relaxation Oscillator with 0.046%/V Voltage and 48.69ppm/°C Temperature Stability for IoT Sensor Node Applications. VLSI Circuits Xiaodong Meng, Xing Li, Xiaopeng Zhong, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki
2019	—	`conf`	A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques. VLSI Circuits Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu
2019	J	`jnl`	A New Rate-Complexity-Distortion Model for Fast Motion Estimation Algorithm in HEVC. IEEE Trans. Multim. Luheng Jia, Chi-Ying Tsui, Oscar C. Au, Kebin Jia
2019	C	`conf`	A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes. ISCAS ChenYang Xia, YouZhe Fan, Chi-Ying Tsui
2019	J	`jnl`	A Two-staged Adaptive Successive Cancellation List Decoding for Polar Codes. CoRR ChenYang Xia, YouZhe Fan, Chi-Ying Tsui
2019	—	`conf`	CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation. ASP-DAC Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2019	J	`jnl`	Design of Sub-Gigahertz Reconfigurable RF Energy Harvester From -22 to 4 dBm With 99.8% Peak MPPT Power Efficiency. IEEE J. Solid State Circuits Zizhen Zeng, Shanpu Shen, Xiaopeng Zhong, Xing Li, Chi-Ying Tsui, Amine Bermak, Ross D. Murch, Edgar Sánchez-Sinencio
2019	J	`jnl`	Microshift: An Efficient Image Compression Algorithm for Hardware. IEEE Trans. Circuits Syst. Video Technol. Bo Zhang, Pedro V. Sander, Chi-Ying Tsui, Amine Bermak
2019	J	`jnl`	SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup. Integr. Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui
2018	J	`jnl`	A 10.6 pJ⋅K IEEE Trans. Circuits Syst. II Express Briefs Bo Wang, Man-Kay Law, Chi-Ying Tsui, Amine Bermak
2018	—	`conf`	A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection. VLSI Circuits Xiaopeng Zhong, Qian Yu, Amine Bermak, Chi-Ying Tsui, May-Kay Law
2018	—	`conf`	A 40.68MHz Active Rectifier with Hybrid Delay Compensation Scheme. APCCAS Langyu Hu, Lin Cheng, Yuan Yao, Tak-Sang Yim, Wing-Hung Ki, Chi-Ying Tsui
2018	J	`jnl`	A Fully Integrated Analog Front End for Biopotential Signal Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. Jiawei Zheng, Wing-Hung Ki, Chi-Ying Tsui
2018	J	`jnl`	A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size. IEEE Trans. Signal Process. ChenYang Xia, Ji Chen, YouZhe Fan, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li
2018	J	`jnl`	A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder with Large List Size. CoRR ChenYang Xia, Ji Chen, YouZhe Fan, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li
2018	J	`jnl`	A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes. CoRR YouZhe Fan, ChenYang Xia, Ji Chen, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li
2018	J	`jnl`	A Low-Power Compression-Based CMOS Image Sensor With Microshift-Guided SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs Xiaopeng Zhong, Bo Zhang, Amine Bermak, Chi-Ying Tsui, Man-Kay Law
2018	—	`conf`	A Simplified PWM Controller for Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier. APCCAS Lin Cheng, Xinyuan Ge, Wing-Hung Ki, Chi-Ying Tsui
2018	—	`conf`	A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization. ASP-DAC Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui
2018	C	`conf`	An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector. ISCAS Xiaodong Meng, Xing Li, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki
2018	J	`jnl`	Analysis and Design of a Ripple Reduction Chopper Bandpass Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. Jiawei Zheng, Wing-Hung Ki, Chi-Ying Tsui
2018	J	`jnl`	Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes. IEEE Trans. Signal Process. Mahsa Mousavi, YouZhe Fan, Chi-Ying Tsui, Jie Jin, Bin Li, Hui Shen
2018	C	`conf`	On Path Memory in List Successive Cancellation Decoder of Polar Codes. ISCAS ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2018	—	`conf`	Polyimide-Based Flexible 3-Coil Inductive Link Design and Optimization. APCCAS Yuan Yao, Xiaodong Meng, Chi-Ying Tsui, Wing-Hung Ki
2018	C	`conf`	Room-Temperature Dual-mode CMOS Gas-FET Sensor for Diabetes Detection. ISCAS Qian Yu, Farid Boussaïd, Amine Bermak, Chi-Ying Tsui
2018	A	`conf`	SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity. DATE Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2017	J	`jnl`	A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier. IEEE J. Solid State Circuits Lin Cheng, Wing-Hung Ki, Chi-Ying Tsui
2017	C	`conf`	A low-offset dynamic comparator with area-efficient and low-power offset cancellation. VLSI-SoC Xiaopeng Zhong, Amine Bermak, Chi-Ying Tsui
2017	—	`conf`	A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applications. ASP-DAC Lin Cheng, Wing-Hung Ki, Chi-Ying Tsui
2017	B	`conf`	An implementation of list successive cancellation decoder with large list size for polar codes. FPL ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, Chongyang Zeng, Jie Jin, Bin Li
2017	—	`conf`	BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques. ASP-DAC Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui
2017	J	`jnl`	Chopper Capacitively Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings. IEEE Trans. Circuits Syst. II Express Briefs Jiawei Zheng, Wing-Hung Ki, Langyu Hu, Chi-Ying Tsui
2017	J	`jnl`	Concatenated LDPC-Polar Codes Decoding Through Belief Propagation. CoRR Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2017	C	`conf`	Concatenated LDPC-polar codes decoding through belief propagation. ISCAS Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2017	C	`conf`	Dual transduction Gas sensor based on a surface acoustic wave resonator. ISCAS Feng Gao, Amine Bermak, Chi-Ying Tsui, Farid Boussaïd
2017	J	`jnl`	High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder. IEEE Trans. Very Large Scale Integr. Syst. Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2017	J	`jnl`	On Path Memory in List Successive Cancellation Decoder of Polar Codes. CoRR ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2017	J	`jnl`	SparseNN: An Energy-Efficient Neural Network Accelerator Exploiting Input and Output Sparsity. CoRR Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2017	J	`jnl`	Wireless Power Transfer System With ΣΔ-Modulated Transmission Power and Fast Load Response for Implantable Medical Devices. IEEE Trans. Circuits Syst. II Express Briefs Xing Li, Yin-Ping Li, Chi-Ying Tsui, Wing-Hung Ki
2016	—	`conf`	21.7 A 6.78MHz 6W wireless power receiver with a 3-level 1× / ½ × / 0× reconfigurable resonant regulating rectifier. ISSCC Lin Cheng, Wing-Hung Ki, Tat-To Wong, Tak-Sang Yim, Chi-Ying Tsui
2016	J	`jnl`	A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes. IEEE J. Sel. Areas Commun. YouZhe Fan, ChenYang Xia, Ji Chen, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li
2016	J	`jnl`	A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu
2016	C	`conf`	A WLAN 2.4-GHz RF energy harvesting system with reconfigurable rectifier for wireless sensor network. ISCAS Zizhen Zeng, Xing Li, Amine Bermak, Chi-Ying Tsui, Wing-Hung Ki
2016	C	`conf`	A low-power chopper bandpass amplifier for biopotential sensors. ISCAS Jiawei Zheng, Wing-Hung Ki, Chi-Ying Tsui
2016	C	`conf`	An indoor solar energy harvesting system using dual mode SIDO converter with fully digital time-based MPPT. ISCAS Xiaodong Meng, Xing Li, Chi-Ying Tsui, Wing-Hung Ki
2016	—	`conf`	Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO. VLSI-SoC (Selected Papers) Syed Mohsin Abbas, Chi-Ying Tsui
2016	J	`jnl`	BiLink: A high performance NoC router architecture using bi-directional link with double data rate. Integr. Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui
2016	J	`jnl`	Hardware Decoders for Polar Codes: An Overview. CoRR Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Burg, Claude Thibeault, Warren J. Gross
2016	C	`conf`	Hardware decoders for polar codes: An overview. ISCAS Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
2016	—	`conf`	LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. ASP-DAC Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui
2016	B	`conf`	Low-Complexity List Successive-Cancellation Decoding of Polar Codes Using List Pruning. GLOBECOM Ji Chen, YouZhe Fan, ChenYang Xia, Chi-Ying Tsui, Jie Jin, Kai Chen, Bin Li
2016	C	`conf`	Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. VLSI-SoC Syed Mohsin Abbas, Chi-Ying Tsui
2016	J	`jnl`	Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling. ACM Trans. Design Autom. Electr. Syst. Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu
2016	—	`ed.`	VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers VLSI-SoC (Selected Papers) Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis
2015	—	`conf`	12.8 Wireless power transfer system using primary equalizer for coupling- and load-range extension in bio-implant applications. ISSCC Xing Li, Chi-Ying Tsui, Wing-Hung Ki
2015	J	`jnl`	A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices. IEEE J. Solid State Circuits Xing Li, Chi-Ying Tsui, Wing-Hung Ki
2015	C	`conf`	A fast variable block size motion estimation algorithm with refined search range for a two-layer data reuse scheme. ISCAS Luheng Jia, Chi-Ying Tsui, Oscar C. Au, Amin Zheng
2015	J	`jnl`	FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels. IEEE Trans. Very Large Scale Integr. Syst. Zhiliang Qian, Syed Mohsin Abbas, Chi-Ying Tsui
2015	J	`jnl`	Low Complexity Belief Propagation Polar Code Decoders. CoRR Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2015	—	`conf`	Low complexity belief propagation polar code decoder. SiPS Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2015	J	`jnl`	Low-latency List Decoding Of Polar Codes With Double Thresholding. CoRR YouZhe Fan, Ji Chen, ChenYang Xia, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li
2015	Misc	`conf`	Low-latency list decoding of polar codes with double thresholding. ICASSP YouZhe Fan, Ji Chen, ChenYang Xia, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li
2015	C	`conf`	Message from the technical program chairs. VLSI-SoC Youngsoo Shin, Chi-Ying Tsui
2015	J	`jnl`	Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier. IEEE Trans. Circuits Syst. I Regul. Pap. Xing Li, Chi-Ying Tsui, Wing-Hung Ki
2015	J	`jnl`	Reconfigurable Resonant Regulating Rectifier With Primary Equalization for Extended Coupling- and Loading-Range in Bio-Implant Wireless Power Transfer. IEEE Trans. Biomed. Circuits Syst. Xing Li, Xiaodong Meng, Chi-Ying Tsui, Wing-Hung Ki
2015	C	`conf`	UHF energy harvesting system using reconfigurable rectifier for wireless sensor network. ISCAS Xing Li, Chi-Ying Tsui, Wing-Hung Ki
2014	—	`conf`	A 13.56MHz wireless power transfer system with reconfigurable resonant regulating rectifier and wireless power control for implantable medical devices. VLSIC Xing Li, Chi-Ying Tsui, Wing-Hung Ki
2014	J	`jnl`	A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System. IEEE Trans. Very Large Scale Integr. Syst. Hui Shao, Xing Li, Chi-Ying Tsui, Wing-Hung Ki
2014	—	`conf`	A comprehensive and accurate latency model for Network-on-Chip performance analysis. ASP-DAC Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu
2014	C	`conf`	A fast intermode decision algorithm based on analysis of inter prediction residual. MMSP Luheng Jia, Oscar C. Au, Chi-Ying Tsui, Wei Dai, Pengfei Wan
2014	J	`jnl`	An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation. IEEE Trans. Signal Process. YouZhe Fan, Chi-Ying Tsui
2014	C	`conf`	An adaptive wireless powering and data telemetry system for optic nerve stimulation. ISCAS Xing Li, Yan Lu, Chi-Ying Tsui, Wing-Hung Ki
2014	—	`conf`	An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms. NOCS Yuankun Xue, Zhiliang Qian, Guopeng Wei, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu
2014	A*	`conf`	Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. DAC Yuankun Xue, Zhiliang Qian, Paul Bogdan, Fan Ye, Chi-Ying Tsui
2014	C	`conf`	Low-latency MAP demapper architecture for coded modulation with iterative decoding. ISCAS YouZhe Fan, Chi-Ying Tsui
2013	—	`conf`	A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices. ISSCC Yan Lu, Xing Li, Wing-Hung Ki, Chi-Ying Tsui, C. Patrick Yue
2013	—	`conf`	A diamond search windowbased adaptive search range algorithm. ICME Workshops Luheng Jia, Oscar C. Au, Chi-Ying Tsui, Yongfang Shi, Rui Ma, Hong Zhang
2013	J	`jnl`	Energy Harvesting and Power Delivery for Implantable Medical Devices. Found. Trends Electron. Des. Autom. Chi-Ying Tsui, Xing Li, Wing-Hung Ki
2013	A	`conf`	Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial). ICCAD Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu
2013	A	`conf`	SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. DATE Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu
2012	A	`conf`	A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels. DATE Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui
2012	—	`conf`	A novel offset cancellation technique for dynamic comparator latch. MWSCAS Ricky Yiu-kee Choi, Chi-Ying Tsui
2012	Misc	`conf`	A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture. CODES+ISSS Zhiliang Qian, Paul Bogdan, Guopeng Wei, Chi-Ying Tsui, Radu Marculescu
2012	—	`conf`	Low-Complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard. VTC Fall YouZhe Fan, Chi-Ying Tsui
2012	—	`ed.`	VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers VLSI-SoC (Selected Papers) Salvador Mir, Chi-Ying Tsui, Ricardo Reis, Oliver C. S. Choy
2011	C	`conf`	A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme. VLSI-SoC Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui
2011	C	`conf`	A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources. VLSI-SoC Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui
2011	C	`conf`	A low-complexity image compression algorithm for Address-Event Representation (AER) PWM image sensors. ISCAS Denis Guangyin Chen, Amine Bermak, Chi-Ying Tsui
2011	—	`conf`	A thermal-aware application specific routing algorithm for Network-on-Chip design. ASP-DAC Zhiliang Qian, Chi-Ying Tsui
2011	—	`conf`	Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications. VLSI-SoC (Selected Papers) Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui
2011	C	`conf`	Design and analysis of on-chip charge pumps for micro-power energy harvesting applications. VLSI-SoC Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui
2011	B	`conf`	Efficient iterative receiver for LDPC coded wireless IPTV system. ICIP YouZhe Fan, James She, Chi-Ying Tsui
2011	J	`jnl`	Low energy multi-stage level converter for sub-threshold logic. IET Comput. Digit. Tech. Hui Shao, Xing Li, Chi-Ying Tsui
2011	J	`jnl`	Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications. IEEE Trans. Very Large Scale Integr. Syst. Chao Lu, Chi-Ying Tsui, Wing-Hung Ki
2010	J	`jnl`	A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor. IEEE J. Solid State Circuits Jun Yin, Jun Yi, Matthew K. Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew M. F. Yuen
2010	C	`conf`	A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control. VLSI-SoC Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2010	—	`conf`	A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor. ISSCC Jun Yin, Jun Yi, Man Kay Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen
2010	J	`jnl`	An Energy Efficient Layered Decoding Architecture for LDPC Decoder. IEEE Trans. Very Large Scale Integr. Syst. Jie Jin, Chi-Ying Tsui
2010	J	`jnl`	Joint Routing and Sleep Scheduling for Lifetime Maximization of Wireless Sensor Networks. IEEE Trans. Wirel. Commun. Feng Liu, Chi-Ying Tsui, Ying Jun Zhang
2010	—	`conf`	Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design. ASP-DAC Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2010	C	`conf`	System level power optimizations for EPC RFID tags to improve sensitivity using load power shaping and operation scheduling. ISCAS Yunxiao Ling, Jun Yi, Chi-Ying Tsui, Wing-Hung Ki
2009	C	`conf`	A Low Energy Two-step Successive Approximation Algorithm for ADC Design. ISCAS Ricky Yiu-kee Choi, Chi-Ying Tsui
2009	A	`conf`	A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications. ISLPED Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2009	—	`conf`	An inductor-less MPPT design for light energy harvesting systems. ASP-DAC Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2009	C	`conf`	Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition. ISCAS Jie Jin, Chi-Ying Tsui
2009	—	`conf`	Low energy level converter design for sub-V ASP-DAC Hui Shao, Chi-Ying Tsui
2009	J	`jnl`	Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation. IEEE J. Solid State Circuits Feng Su, Wing-Hung Ki, Chi-Ying Tsui
2009	J	`jnl`	The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control. IEEE Trans. Very Large Scale Integr. Syst. Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2008	—	`conf`	A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. ISQED Ricky Yiu-kee Choi, Chi-Ying Tsui
2008	J	`jnl`	A Single-Chip UHF RFID Reader in 0.18 µm CMOS Process. IEEE J. Solid State Circuits Wenting Wang, Shuzuo Lou, Kay W. C. Chui, Sujiang Rong, Chi Fung Lok, Hui Zheng, Hin-Tat Chan, Sau-Wing Man, Howard C. Luong, Vincent K. N. Lau, Chi-Ying Tsui
2008	A	`conf`	A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes. ISLPED Jie Jin, Chi-Ying Tsui
2008	C	`conf`	An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting. ISCAS Jun Yi, Feng Su, Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui
2008	C	`conf`	Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications. ISCAS Ngok-Man Sze, Feng Su, Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui
2008	J	`jnl`	Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping. Integr. Chi-Ying Tsui, Robert Yi-Ching Au, Ricky Yiu-kee Choi
2008	—	`conf`	Threshold Voltage Start-up Boost Converter for Sub-mA Applications. DELTA Ngok-Man Sze, Wing-Hung Ki, Chi-Ying Tsui
2008	J	`jnl`	Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications. IEEE J. Solid State Circuits Feng Su, Wing-Hung Ki, Chi-Ying Tsui
2007	J	`jnl`	A IEEE Trans. Circuits Syst. II Express Briefs Hing Mo Lam, Chi-Ying Tsui
2007	C	`conf`	A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications. ISCAS Chao Lu, Chi-Ying Tsui, Wing-Hung Ki
2007	Misc	`conf`	A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. VLSI Design Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao
2007	A	`conf`	A micro power management system and maximum output power control for solar energy harvesting applications. ISLPED Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2007	—	`conf`	A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic. ESSCIRC Hui Shao, Chi-Ying Tsui
2007	C	`conf`	An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications. ISCAS Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2007	J	`jnl`	Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Jun Yi, Wing-Hung Ki, Chi-Ying Tsui
2007	J	`jnl`	Corrections to "Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications" [Jan 07 153-166]. IEEE Trans. Circuits Syst. I Regul. Pap. Jun Yi, Wing-Hung Ki, Chi-Ying Tsui
2007	C	`conf`	Design and Implementation of a Low-power Baseband-system for RFID Tag. ISCAS Adam S. W. Man, Edward S. Zhang, Hin-Tat Chan, Vincent K. N. Lau, Chi-Ying Tsui, Howard C. Luong
2007	A*	`conf`	Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. DAC Lap-Fai Leung, Chi-Ying Tsui
2007	J	`jnl`	Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling CoRR Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
2007	J	`jnl`	Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. IEEE Trans. Very Large Scale Integr. Syst. Jie Jin, Chi-Ying Tsui
2007	—	`conf`	Single-Chip UHF RFID reader in 0.18- μm CMOS. CICC Wenting Wang, Shuzuo Lou, Kay W. C. Chui, Sujiang Rong, Chi Fung Lok, Hui Zheng, Hin-Tat Chan, Adam S. W. Man, Howard C. Luong, Vincent Kin Nang Lau, Chi-Ying Tsui
2007	A	`conf`	Vibration energy scavenging and management for ultra low power applications. ISLPED Chao Lu, Chi-Ying Tsui, Wing-Hung Ki
2006	C	`conf`	A charge based computation system and control strategy for energy harvesting applications. ISCAS Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
2006	A	`conf`	A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications. ISLPED Jie Jin, Chi-Ying Tsui
2006	—	`conf`	Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. ASP-DAC Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui
2006	C	`conf`	Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time. ISCAS Feng Liu, Chi-Ying Tsui
2006	C	`conf`	High efficiency cross-coupled doubler with no reversion loss. ISCAS Feng Su, Wing-Hung Ki, Chi-Ying Tsui
2006	C	`conf`	High performance single clock cycle CMOS comparator. ISCAS Hing-Mo Lam, Chi-Ying Tsui
2006	J	`jnl`	Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices. IEEE Trans. Circuits Syst. II Express Briefs Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui
2006	—	`conf`	Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. ASP-DAC Yat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui
2006	—	`conf`	Low Complexity SST Viterbi Decoder. VTC Fall Jin Jie, Chi-Ying Tsui
2006	A*	`conf`	Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. DAC Lap-Fai Leung, Chi-Ying Tsui
2006	—	`conf`	Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. ASP-DAC Chi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su
2005	—	`conf`	A Data Discarding Framework for Reducing the Energy Consumption of Viterbi Decoder in Decoding Broadcasted Wireless Multi-Resolution JPEG2000 Images. ESTIMedia Feng Liu, Chi-Ying Tsui
2005	J	`jnl`	A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation. IEEE J. Solid State Circuits Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui
2005	—	`conf`	A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems. ISCAS (4) Jin Jie, Chi-Ying Tsui, Wai Ho Mow
2005	—	`conf`	Charge redistribution loss consideration in optimal charge pump design. ISCAS (2) Wing-Hung Ki, Feng Su, Chi-Ying Tsui
2005	A	`conf`	Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. DATE Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
2005	—	`conf`	Gate control strategies for high efficiency charge pumps. ISCAS (2) Feng Su, Wing-Hung Ki, Chi-Ying Tsui
2004	—	`conf`	A dual-band switching digital controller for a buck converter. ASP-DAC Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui
2004	—	`conf`	Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication. ESTIMedia Feng Liu, Chi-Ying Tsui
2004	J	`jnl`	An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction. IEEE J. Solid State Circuits Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui
2004	—	`conf`	Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus. ISCAS (2) Siu-Kei Wong, Chi-Ying Tsui
2004	—	`conf`	Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling. PATMOS Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
2004	—	`conf`	Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process. ASP-DAC Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui
2004	—	`conf`	Least leakage vector assisted technology mapping for total power optimization. ISCAS (5) Robert Yi-Ching Au, Chi-Ying Tsui
2004	—	`conf`	Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data. ASP-DAC Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
2004	—	`conf`	Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment. ASP-DAC Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
2004	—	`conf`	Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity. ASP-DAC Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow
2004	A	`conf`	Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus. DATE Siu-Kei Wong, Chi-Ying Tsui
2003	J	`jnl`	A pseudo-CCM/DCM SIMO switching converter with freewheel switching. IEEE J. Solid State Circuits Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui
2003	—	`conf`	Design and implementation of high-speed arbiter for large scale VOQ crossbar switches. ISCAS (2) Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui
2003	—	`conf`	High performance and low power completion detection circuit. ISCAS (5) Hing-Mo Lam, Chi-Ying Tsui
2003	—	`conf`	Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming. ISCAS (5) Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
2003	—	`conf`	Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation. ISCAS (3) Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok
2003	J	`jnl`	Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode. IEEE J. Solid State Circuits Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok
2002	—	`conf`	A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels. ISCAS (3) Kwan-wai Wong, Chi-Ying Tsui, Roger S.-K. Cheng, Wai Ho Mow
2002	—	`conf`	Low complexity OFDM receiver using Log-FFT for coded OFDM system. ISCAS (3) Yan Wang, Hing Mo Lam, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow
2002	—	`conf`	Performance study of OFDM receiver using FFT based on log number system. VTC Spring Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow
2002	—	`conf`	Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches. Hot Interconnects Jing Liu, Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui
2001	—	`conf`	A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. ASP-DAC Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok
2001	J	`jnl`	Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S.-K. Cheng
2001	—	`conf`	Single-inductor multiple-output switching converters with bipolar outputs. ISCAS (3) Dongsheng Ma, Wing-Hung Ki, Philip K. T. Mok, Chi-Ying Tsui
2000	B	`conf`	A low complexity architecture of the V-BLAST system. WCNC Wong Kwan Wai, Chi-Ying Tsui, Roger S. Cheng
2000	C	`conf`	A low power VLSI architecture of SOVA-based turbo-code decoder using scarce state transition scheme. ISCAS Yan Wang, Chi-Ying Tsui, Roger S. Cheng
2000	Misc	`conf`	A reduced complexity implementation of the Log-Map algorithm for turbo-codes decoding. ICASSP Yan Wang, Chi-Ying Tsui, Roger Shu-Kwan Cheng
2000	B	`conf`	Composite interference cancellation scheme for CDMA systems. GLOBECOM Billy Chi-Kin Poon, Chi-Ying Tsui, Roger S. Cheng
2000	J	`jnl`	Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications. Wirel. Pers. Commun. Chi-Ying Tsui, Roger S.-K. Cheng, Curtis Ling
2000	C	`conf`	Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme. ISCAS Bob Ka-Man Wong, Chi-Ying Tsui, Roger S.-K. Cheng
2000	J	`jnl`	Low-power VLSI design for motion estimation using adaptive pixel truncation. IEEE Trans. Circuits Syst. Video Technol. Zhong-Li He, Chi-Ying Tsui, Kai-Keung Chan, Ming L. Liou
2000	—	`conf`	VLSI implementation of a switch fabric for mixed ATM and IP traffic. ASP-DAC Chi-Ying Tsui, Louis Chung-Yin Kwan, Chin-Tau Lea
2000	—	`conf`	VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA. ASP-DAC Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S. Cheng
1999	J	`jnl`	A/I Net: a network that integrates ATM and IP. IEEE Netw. Chin-Tau Lea, Chi-Ying Tsui, Bo Li, C.-Y. Kwan, Stanley K.-M. Chan, Angus H.-W. Chan
1999	B	`conf`	Adaptive tracking of optimal bit and power allocation for OFDM systems in time-varying channels. WCNC Sai Kit Lai, Roger S. Cheng, Khaled Ben Letaief, Chi-Ying Tsui
1999	—	`conf`	An Integrated Battery-Hardware Model for Portable Electronics. ASP-DAC Massoud Pedram, Chi-Ying Tsui, Qing Wu
1999	—	`conf`	Finite state machine partitioning for low power. ISCAS (1) Wai-Kwong Lee, Chi-Ying Tsui
1999	—	`conf`	Low power ACS unit design for the Viterbi decoder [CDMA wireless systems]. ISCAS (1) Chi-Ying Tsui, Roger Shu-Kwan Cheng, Curtis Ling
1999	A	`conf`	Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. ISLPED Oliver Yuk-Hang Leung, Chung-Wai Yue, Chi-Ying Tsui, Roger S. Cheng
1999	—	`conf`	Timing Optimization of Logic Network Using Gate Duplication. ASP-DAC Chun-Hong Chen, Chi-Ying Tsui
1999	—	`conf`	Unequal error protection for wireless transmission of MPEG audio. ISCAS (6) Chi Wai Yung, Hung Fai Fu, Chi-Ying Tsui, Roger S. Cheng, D. George
1998	J	`jnl`	Accurate and efficient power simulation strategy by compacting the input vector set. Integr. Chi-Ying Tsui, Massoud Pedram
1998	J	`jnl`	Gate-level power estimation using tagged probabilistic simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
1998	J	`jnl`	Generic VLSI architecture for block-matching motion estimation algorithms. Int. J. Imaging Syst. Technol. Zhong-Li He, Ming L. Liou, Philip C. H. Chan, Chi-Ying Tsui
1998	J	`jnl`	Low-power state assignment targeting two- and multilevel logic implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1998	A	`conf`	Towards the capability of providing power-area-delay trade-off at the register transfer level. ISLPED Chun-Hong Chen, Chi-Ying Tsui
1997	A*	`conf`	A Power Estimation Framework for Designing Low Power Portable Video Applications. DAC Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram
1997	Misc	`conf`	An efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms. ICASSP Xiao-Dong Zhang, Chi-Ying Tsui
1997	A	`conf`	Low power motion estimation design using adaptive pixel truncation. ISLPED Zhong-Li He, Kai-Keung Chan, Chi-Ying Tsui, Ming L. Liou
1996	J	`jnl`	Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. Very Large Scale Integr. Syst. Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
1996	A*	`conf`	Improving the Efficiency of Power Simulators by Input Vector Compaction. DAC Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram
1995	J	`jnl`	Power estimation methods for sequential logic circuits. IEEE Trans. Very Large Scale Integr. Syst. Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
1994	A*	`conf`	Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. DAC Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1994	A	`conf`	Low power state assignment targeting two-and multi-level logic implementations. ICCAD Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
1994	—	`conf`	Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. COMPCON Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
1994	J	`jnl`	Power efficient technology decomposition and mapping under an extended power consumption model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1994	J	`jnl`	Saving Power in the Control Path of Embedded Processors. IEEE Des. Test Comput. Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
1993	A	`conf`	Efficient estimation of dynamic power consumption under a real delay model. ICCAD Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1993	A*	`conf`	Technology Decomposition and Mapping Targeting Low Power Dissipation. DAC Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1992	A*	`conf`	Application-Driven Design Automation for Microprocessor Design. DAC Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain