Chi-Hsiang Huang

11 papers Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery.
IEEE J. Solid State Circuits
Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Kevin Patino-Sosa, Philip Anschutz, Amanda L. Jacob, Keshav Ramachandra, Samuel J. Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe
2025 — conf
A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery.
CICC
Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Philip Anschutz, Amanda L. Jacob, Keshav Ramachandra, Samuel J. Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe
2023 J jnl
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains.
IEEE J. Solid State Circuits
Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe
2022 — conf
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS.
ISSCC
Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe
2022 — conf
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains.
ISSCC
Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe
2022 J jnl
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control.
IEEE J. Solid State Circuits
Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe
2021 — conf
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS.
ISSCC
Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe
2020 — conf
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.
VLSI Circuits
Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe
2020 — conf
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.
VLSI Circuits
Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe
2019 J jnl
Bidirectional Single-Inductor Dual-Supply Converter With Automatic State-Transition for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hung-Hsien Wu, Chi-Hsiang Huang, Chia-Ling Wei, Jih-Sheng Lai
2018 J jnl
Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter.
IEEE J. Solid State Circuits
Chi-Hsiang Huang, Hung-Hsien Wu, Chia-Ling Wei