Chi-Feng Wu - RankMe

30 papers A* 1A 3Misc 1Journal 13Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Study on the Enhancement Mechanism for Identifying Annotations on Ultrasound Images. MedInfo Cheng-Jung Wu, Yu-Chih Wei, Chi-Feng Wu
2017	—	`conf`	Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu
2014	—	`conf`	Apply high-level synthesis design and verification methodology on floating-point unit implementation. VLSI-DAT Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu
2014	A	`conf`	Mask-cost-aware ECO routing DATE Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang
2013	—	`conf`	Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu
2012	J	`jnl`	Applying a Functional Neurofuzzy Network to Real-Time Lane Detection and Front-Vehicle Distance Measurement. IEEE Trans. Syst. Man Cybern. Part C Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee
2012	J	`jnl`	Locating Text in Images Based on the Smooth Gray-Level Detection. Int. J. Image Graph. Shiueng-Bien Yang, Chi-Feng Wu
2012	—	`conf`	Test for more than pass/fail using on-chip temperature sensor. VLSI-DAT Chih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu
2011	J	`jnl`	A functional neural fuzzy network for classification applications. Expert Syst. Appl. Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee
2009	A	`conf`	A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. ITC Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu
2009	J	`jnl`	Application of neural networks and genetic algorithms to the screening for high quality chips. Appl. Soft Comput. Chenn-Jung Huang, You-Jia Chen, Chi-Feng Wu, Yi-an Huang
2007	—	`conf`	CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. ATS Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu
2004	J	`jnl`	A novel approach to enable decorrelating multiuser detection without matrix inversion operations. Int. J. Commun. Syst. Hsiao-Hwa Chen, Chi-Feng Wu
2003	J	`jnl`	Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
2003	J	`jnl`	Isotropic air-interface technologies for fourth generation wireless communications. Wirel. Commun. Mob. Comput. Hsiao-Hwa Chen, Jin-Xiao Lin, Shin-Wei Chu, Chi-Feng Wu, Guo-Sheng Chen
2002	J	`jnl`	A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electron. Test. Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
2002	J	`jnl`	Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
2002	—	`conf`	Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2002	J	`jnl`	Image Processing Techniques for Wafer Defect Cluster Identification. IEEE Des. Test Comput. Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu
2001	—	`conf`	A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
2001	A*	`conf`	Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
2000	—	`conf`	A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
2000	—	`conf`	Collaboration between Industry and Academia in Test Research. Asian Test Symposium Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
2000	A	`conf`	Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
2000	Misc	`conf`	Simulation-Based Test Algorithm Generation for Random Access Memories. VTS Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
2000	J	`jnl`	Single-ended SRAM with high test coverage and short test time. IEEE J. Solid State Circuits Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao
2000	J	`jnl`	Testing and Diagnosing Dynamic Reconfigurable FPGA. VLSI Design Chi-Feng Wu, Cheng-Wen Wu
1999	J	`jnl`	A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
1999	—	`conf`	RAMSES: A Fast Memory Fault Simulator. DFT Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
1999	—	`conf`	Testing Interconnects of Dynamic Reconfigurable FPGAs. ASP-DAC Chi-Feng Wu, Cheng-Wen Wu