Chi-Chou Kao

28 papers C 1Journal 21Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
An Improved Graph Convolutional Network Model Integrating Hadamard Product and Virtual Edge Features for Intelligent Transportation.
Int. J. Intell. Transp. Syst. Res.
Chi-Chou Kao, Hung-Yi Lin
2025 J jnl
Optimizing Layout Synthesis for Quantum Computing Performance.
J. Circuits Syst. Comput.
Chi-Chou Kao, Hung-Yi Lin
2024 J jnl
Performance-Oriented Layout Synthesis for Quantum Computing.
Comput. Syst. Sci. Eng.
Chi-Chou Kao, Hung-Yi Lin
2023 J jnl
Optimizing FPGA-Based Convolutional Neural Network Performance.
J. Circuits Syst. Comput.
Chi-Chou Kao
2023 J jnl
Performance-oriented FPGA-based convolution neural network designs.
Multim. Tools Appl.
Chi-Chou Kao
2020 J jnl
Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding.
Multim. Tools Appl.
Chi-Chou Kao
2020 J jnl
Resource and Performance Tradeoff for Task Scheduling of Parallel Reconfigurable Architectures.
J. Circuits Syst. Comput.
Chi-Chou Kao
2019 J jnl
Design and Implementation of Stereoscopic Image Generation.
J. Circuits Syst. Comput.
Chi-Chou Kao
2017 J jnl
Designs of Low Power Snoop for Multiprocessor System on Chip.
J. Signal Process. Syst.
Chi-Chou Kao, Yi-Ciang Lin
2017 J jnl
Stereoscopic image generation with depth image based rendering.
Multim. Tools Appl.
Chi-Chou Kao
2015 J jnl
Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction.
J. Signal Process. Syst.
Chi-Chou Kao
2015 J jnl
Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable Architectures.
IEEE Trans. Parallel Distributed Syst.
Chi-Chou Kao
2013 — conf
E-Health Design of EEG Signal Classification for Epilepsy Diagnosis.
ISBAST
Chi-Chou Kao
2013 J jnl
Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs.
J. Circuits Syst. Comput.
Chi-Chou Kao, Yen-Tai Lai
2012 — conf
Laplacian-based H.264 intra-prediction mode decision.
CHINACOM
Chi-Chou Kao, Yen-Tai Lai, Chao-Feng Tseng
2011 J jnl
BDD-based synthesis for mixed CMOS/PTL logic.
Int. J. Circuit Theory Appl.
Chi-Chou Kao
2011 J jnl
Heuristic Algorithms for Constructing Interference-Free and Delay-Constrained Multicast Trees for Wireless Mesh Networks.
KSII Trans. Internet Inf. Syst.
Wen-Lin Yang, Chi-Chou Kao, Cheng-Huang Tung
2010 J jnl
A Performance-Driven Rotational Invariant Image Retrieval System.
J. Inf. Sci. Eng.
Yen-Tai Lai, Chi-Chou Kao, Tzu-Chiang Tai, Wen-Chun Yeh
2010 J jnl
An efficient reflection invariance region-based image retrieval framework.
Int. J. Imaging Syst. Technol.
Chi-Chou Kao, Yen-Tai Lai, Chia-Hui Lin
2009 C conf
A Novel Digital Pixel Sensor System.
ISCAS
Yen-Tai Lai, Chia-Nan Yeh, Chi-Chou Kao
2008 J jnl
Computer-aided crosstalk minimisation design for system-on-chip.
IET Comput. Digit. Tech.
Chi-Chou Kao
2007 J jnl
A High Flexibility Design for Clock Distribution Network in System on Chip.
J. Circuits Syst. Comput.
Chi-Chou Kao
2005 J jnl
An efficient algorithm for finding the minimal-area FPGA technology mapping.
ACM Trans. Design Autom. Electr. Syst.
Chi-Chou Kao, Yen-Tai Lai
2004 — conf
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.
ASP-DAC
Chi-Chou Kao, Yen-Tai Lai
2003 — conf
A technology mapping algorithm for heterogeneous FPGAs.
ASP-DAC
Chi-Chou Kao, Yen-Tai Lai
2003 J jnl
Design of echo cancellation and noise elimination for speech enhancement.
IEEE Trans. Consumer Electron.
Chi-Chou Kao
1999 — conf
A quadratic programming method for interconnection crosstalk minimization.
ISCAS (6)
Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh
1999 — conf
A routability and performance driven technology mapping algorithm for LUT based FPGA designs.
ISCAS (1)
Chi-Chou Kao, Yen-Tai Lai