Chi-Chang Lu

23 papers C 3Journal 7Unranked 13
YearRankTypeTitle / Venue / Authors
2020 J jnl
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme.
IEEE Access
Chi-Chang Lu, Ding-Ke Huang
2020 J jnl
A High-Precision Bandgap Reference With a V-Curve Correction Circuit.
IEEE Access
Chang-Chi Lee, Hou-Ming Chen, Chi-Chang Lu, Bo-Yi Lee, Hsien-Chi Huang, He-Sheng Fu, Yong-Xin Lin
2019 J jnl
1.2 V 10-bits 40 MS/s CMOS SAR ADC for low-power applications.
IET Circuits Devices Syst.
Chi-Chang Lu, Ding-Ke Huang
2019 — conf
Capacitive digital-to-analog converter for low-power SAR ADCs.
ICCE-TW
Chi-Chang Lu, Sheng-Yan Lai
2018 — conf
Intelligent Infant Monitoring System Involving a Wi-Fi Wireless Sensor Network.
IIH-MSP (2)
Chi-Chang Lu, Chung-Hsien Wu, Hui-Kai Su
2015 — conf
A Study of the Accessible Approach to Replace the Reservoir Silt Glaze with New Formula.
HCI (12)
Chi-Chang Lu, Po-Hsien Lin
2014 — conf
Cultural Creativity in Design Strategy: A Case Study of User's Preference of a Bird-Shaped Teapot.
HCI (19)
Chi-Chang Lu, Po-Hsien Lin
2013 C conf
A 1.2V 10-bit 5 MS/s CMOS cyclic ADC.
ISCAS
Chi-Chang Lu
2013 — conf
Research on Symbol Expression for Eye Image in Product Design: The Usage of the Chinese Traditional "Yun Wen".
HCI (20)
Chi-Chang Lu, Po-Hsien Lin
2011 J jnl
A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit.
Circuits Syst. Signal Process.
Tsung-Sum Lee, Chi-Chang Lu
2011 — conf
A Study of Producing Ceramic Glaze Utilizing Shihmen Reservoir Silt.
HCI (15)
Chi-Chang Lu, Po-Hsien Lin
2011 — conf
Design for Aesthetic Experience.
HCI (15)
Po-Hsien Lin, Chi-Chang Lu, Mo-Li Yeh
2010 C conf
A 1.5V 12-b 40 MSamples/s CMOS pipelined ADC.
ISCAS
Chi-Chang Lu, Wei-Xiang Tung
2010 — conf
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
CICC
Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu
2010 J jnl
Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers.
Circuits Syst. Signal Process.
Tsung-Sum Lee, Chi-Chang Lu
2008 — conf
A CMOS low-voltage fully differential sample-and-hold circuit.
APCCAS
Chi-Chang Lu, Wei-Xiang Tung, Chien-Kuo Huang
2007 C conf
A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter.
ISCAS
Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee
2007 J jnl
A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter.
IEEE Trans. Circuits Syst. II Express Briefs
Chi-Chang Lu, Tsung-Sum Lee
2007 — conf
A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuit.
SoCC
Tsung-Sum Lee, Chi-Chang Lu, Jian-Ting Zhan
2005 J jnl
A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tsung-Sum Lee, Chi-Chang Lu
2005 — conf
A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal.
ISCAS (4)
Tsung-Sum Lee, Chi-Chang Lu, Shen-Hau Yu, Jian-Ting Zhan
2003 — conf
A fully differential low-voltage CMOS high-speed track-and-hold circuit.
ISCAS (1)
Tsung-Sum Lee, Chi-Chang Lu
2002 — conf
A low-voltage fully differential CMOS high-speed track-and-hold circuit.
APCCAS (1)
Tsung-Sum Lee, Chi-Chang Lu