Chewnpu Jou

29 papers C 2Journal 6Unranked 21
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage.
IEEE Access
Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2024 — conf
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process.
AICAS
Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2022 — conf
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture.
APCCAS
Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu
2019 J jnl
A 0.85mm
IEEE J. Solid State Circuits
Kai Xu, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
2019 — conf
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
ESSCIRC
Feng-Wei Kuo, Zhirui Zong, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
2019 J jnl
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications.
IEEE J. Solid State Circuits
Yanghyo Rod Kim, Boyu Hu, Yuan Du, Wei-Han Cho, Rulin Huang, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang
2018 — conf
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications.
ISSCC
Yanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang
2018 J jnl
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
2017 J jnl
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits
Feng-Wei Kuo, Sandro Binsfeld Ferreira, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Iman Madadi, Massoud Tohidian, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski
2016 — conf
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
ISSCC
Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2016 — conf
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS.
ISSCC
Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2016 — conf
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
VLSI Circuits
Feng-Wei Kuo, Sandro Binsfeld Ferreira, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski
2016 J jnl
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm.
IEEE J. Solid State Circuits
Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski
2015 — conf
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB.
ISSCC
Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang
2015 — conf
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm.
ESSCIRC
Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski
2015 — conf
Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology.
3DIC
Chuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Chang, En-Hsiang Yeh, Feng-Wei Kuo, Hsu-Hsien Chen, Chih-Hua Chen, Huan-Neng Ron Chen, Ying-Ta Lu, Chewnpu Jou, Hao-Yi Tsai, C. S. Liu, Doug C. H. Yu
2014 — conf
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS.
VLSIC
Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski
2014 C conf
ESD protection design for wideband RF applications in 65-nm CMOS process.
ISCAS
Li-Wei Chu, Chun-Yu Lin, Ming-Dou Ker, Ming-Hsiang Song, Jeng-Chou Tseng, Chewnpu Jou, Ming-Hsien Tsai
2013 — conf
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.
ISSCC
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013 — conf
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing.
ISSCC
I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh
2012 — conf
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration.
CICC
Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
2012 — conf
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression.
ISSCC
Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
2012 C conf
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology.
ISCAS
Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsiang Song, Chewnpu Jou, Tse-Hua Lu, Jeng-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang
2012 — conf
Session 24 overview: 10GBase-T and optical front ends: Wireline subcommittee.
ISSCC
Miki Moyal, Chewnpu Jou
2011 — conf
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.
ISSCC
Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang
2010 — conf
A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS.
CICC
Hsieh-Hung Hsieh, Fu-Lung Hsueh, Chewnpu Jou, Fred Kuo, Sean Chen, Tzu-Jin Yeh, Kevin Kai-Wen Tan, Po-Yi Wu, Yu-Ling Lin, Ming-Hsien Tsai
2010 — conf
A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX.
ESSCIRC
David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang
2010 — conf
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example.
ASP-DAC
W. M. Young, Chua-Huang Huang, Alan P. Su, Chewnpu Jou, Fu-Lung Hsueh
2010 — conf
D-band CMOS transmitter and receiver for multi-giga-bit/sec wireless data link.
CICC
Zhiwei Xu, Qun Jane Gu, Yi-Cheng Wu, Adrian Tang, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang