Chetan Kumar Vudadha

23 papers C 4Misc 3Journal 6Unranked 10
YearRankTypeTitle / Venue / Authors
2024 C conf
Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation.
ISCAS
Chetan Kumar Vudadha
2024 J jnl
Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation.
J. Circuits Syst. Comput.
Vikas Shivakumar, Chetan Kumar Vudadha
2024 J jnl
Design of a Ternary Logic Processor Using CNTFET Technology.
Circuits Syst. Signal Process.
Sharvani Gadgil, Goli Naga Sandesh, Chetan Kumar Vudadha
2023 J jnl
Power efficient designs of CNTFET-based ternary SRAM.
Microelectron. J.
Sharvani Gadgil, Goli Naga Sandesh, Chetan Kumar Vudadha
2022 — conf
Design of CNTFET-based Ternary Logic circuits using Low power Encoder.
iSES
Siddharth T, Sharvani Gadgil, Chetan Kumar Vudadha
2022 — conf
Evaluation of x86 and ARM architectures using compute-intensive workloads.
iSES
S. Vignesh Bharadwaj, Chetan Kumar Vudadha
2022 J jnl
Optimization of Reversible Circuits Using Gate Pair Classification.
SN Comput. Sci.
P. Sai Phaneendra, Chetan Kumar Vudadha, M. B. Srinivas
2020 Misc conf
A Novel Low Power Ternary Multiplier Design using CNFETs.
VLSID
Harita Sirugudi, Sharvani Gadgil, Chetan Kumar Vudadha
2020 C conf
FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design.
ISCAS
P. Veda Bhanu, Chetan Kumar Vudadha, J. Soumya
2019 — conf
Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs.
iSES
Poojan Patel, Nikita Doddapaneni, Sharvani Gadgil, Chetan Kumar Vudadha
2018 — conf
Design Methodologies for Ternary Logic Circuits.
ISMVL
Chetan Kumar Vudadha, M. B. Srinivas
2018 J jnl
Energy efficient design of CNFET-based multi-digit ternary adders.
Microelectron. J.
Chetan Kumar Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas
2018 J jnl
Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chetan Kumar Vudadha, Ajay Surya, Saurabh Agrawal, M. B. Srinivas
2017 C conf
An ESOP Based Cube Decomposition Technique for Reversible Circuits.
RC
Sai Phaneendra Parlapalli, Chetan Kumar Vudadha, M. B. Srinivas
2017 C conf
Optimizing the Reversible Circuits Using Complementary Control Line Transformation.
RC
Sai Phaneendra Parlapalli, Chetan Kumar Vudadha, M. B. Srinivas
2016 — conf
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits.
iNIS
Chetan Kumar Vudadha, P. Sai Phaneendra, M. B. Srinivas
2014 — conf
A New Design of an N-Bit Reversible Arithmetic Logic Unit.
ISED
Subhankar Pal, Chetan Kumar Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika
2014 Misc conf
An Optimized Design of Reversible Quantum Comparator.
VLSID
P. Sai Phaneendra, Chetan Kumar Vudadha, Sreehari Veeramachaneni, M. B. Srinivas
2012 — conf
CNFET based ternary magnitude comparator.
ISCIT
Chetan Kumar Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas
2012 — conf
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 — conf
Design of Prefix-Based Optimal Reversible Comparator.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 Misc conf
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
VLSI Design
Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
ISCIT
P. Sai Phaneendra, Chetan Kumar Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas