Chetan D. Parikh

15 papers A 1Misc 2Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2021 J jnl
Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches.
Circuits Syst. Signal Process.
Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen
2021 Misc conf
Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients.
VLSID
Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen
2021 — conf
Digital Calibration of 1.5 bits/stage Algorithmic ADC.
ISOCC
Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen
2020 — conf
High Performance Operational Amplifier with 90dB Gain in SCL 180nm Technology.
VDAT
Surya Padma, Sounak Das, Subhajit Sen, Chetan D. Parikh
2019 — conf
Wake-up circuit for PAM4 receiver.
ISED
Vamsi Krishna Guduru, Richa Gupta, Bhavani Lakshmi Polareddy, M. Anish Unnikrishnan, Chetan D. Parikh, Subhajit Sen
2018 Misc conf
A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs.
VLSID
Uma Mukund Kulkarni, Chetan D. Parikh, Subhajit Sen
2017 — conf
A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage.
VDAT
Pallavi G. Darji, Chetan D. Parikh
2016 — conf
New technique to improve transient response of LDO regulators without an off-chip capacitor.
VDAT
Chetan D. Parikh, Gopal Agarwal
2016 J jnl
Novel Analog Calibration Technique for Current-Steering DACs' Dynamic Performance.
Circuits Syst. Signal Process.
Pallavi G. Darji, Chetan D. Parikh
2015 J jnl
A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators.
Circuits Syst. Signal Process.
A. Purushothaman, Chetan D. Parikh
2015 J jnl
A low power low area capacitor array based Digital to Analog Converter architecture.
Microelectron. J.
A. Purushothaman, Chetan D. Parikh
2015 J jnl
Novel Analog Calibration Technique for Current-Steering DACs.
Circuits Syst. Signal Process.
Pallavi G. Darji, Chetan D. Parikh
2013 — conf
10 Gbps Current Mode Logic I/O Buffer.
VDAT
Akhil Rathore, Chetan D. Parikh
2013 — conf
A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier.
VDAT
Vivek Verma, Chetan D. Parikh
2008 A conf
Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation.
ISLPED
Shagun Bajoria, Vineet Kumar Singh, Raju Kunde, Chetan D. Parikh