Chester Liu

14 papers A* 1Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
Energy-Efficient Parallel Interconnects for Chiplet Integration.
IEEE Micro
Wei Tang, Chester Liu, Zhengya Zhang
2022 — conf
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.
VLSI Technology and Circuits
Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang
2021 — conf
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer.
CICC
Chester Liu, Jacob Botimer, Zhengya Zhang
2021 — conf
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA.
VLSI Circuits
Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang
2021 J jnl
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference.
IEEE J. Solid State Circuits
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
2019 J jnl
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification.
IEEE J. Solid State Circuits
Thomas Chen, Ching-En Lee, Chester Liu, Zhengya Zhang
2019 — conf
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS.
VLSI Circuits
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
2018 J jnl
A 2.56-mm
IEEE J. Solid State Circuits
Chester Liu, Sung-Gun Cho, Zhengya Zhang
2018 — conf
Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm.
BioCAS
Chester Liu, Zhengya Zhang
2017 — conf
A 2.56mm
A-SSCC
Chester Liu, Sung-Gun Cho, Zhengya Zhang
2016 — conf
A 1.40mm
VLSI Circuits
Phil Knag, Chester Liu, Zhengya Zhang
2013 — conf
Implementation of a highly scalable blokus duo solver on FPGA.
FPT
Chester Liu
2011 J jnl
Placement Optimization of Flexible TFT Digital Circuits.
IEEE Des. Test Comput.
Chester Liu, En-Hua Ma, Wen-En Wei, Chien-Mo James Li, I-Chun Cheng, Yung-Hui Yeh
2010 A* conf
Static timing analysis for flexible TFT circuits.
DAC
Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li