Chenyun Pan

44 papers A* 1A 1C 1Journal 22Unranked 19
YearRankTypeTitle / Venue / Authors
2026 J jnl
Novel FPGA Technology Mapping for Dual-Output LUTs: Methodology and Application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liuting Shang, Sheng Lu, Sungyong Jung, Qilian Liang, Chenyun Pan
2025 J jnl
A Novel RFET-Based FPGA Architecture Based on Delay-Aware Packing Algorithm.
IEEE Trans. Emerg. Top. Comput.
Sheng Lu, Liuting Shang, Sungyong Jung, Qilian Liang, Chenyun Pan
2025 J jnl
An Energy-Efficient RFET-Based Stochastic Computing Neural Network Accelerator.
CoRR
Sheng Lu, Qianhou Qu, Sungyong Jung, Qilian Liang, Chenyun Pan
2025 — conf
Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node.
ISQED
Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Qilian Liang, Chenyun Pan
2025 J jnl
Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Prashant Dubey, Chenyun Pan
2025 C conf
QPUF 2.0: Exploring Quantum Physical Unclonable Functions for Security-by-Design of Energy Cyber-Physical Systems.
WoWMoM
Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos
2025 J jnl
QPUF 2.0: Exploring Quantum Physical Unclonable Functions for Security-by-Design of Energy Cyber-Physical Systems.
IEEE Internet Things J.
Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos
2025 — conf
QPUF 3.0: Sustainable Cybersecurity of Smart Grid through Security-By-Design based on Quantum-PUF and Quantum Key Distribution.
ACM Great Lakes Symposium on VLSI
Venkata Karthik Vishnu Vardhan Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos
2025 J jnl
QPUF: Quantum Physical Unclonable Functions for Security-by-Design of Industrial Internet-of-Things.
Cryptogr.
Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos
2025 J jnl
Sneak Path Current Modeling in Memristor Crossbar Arrays for Analog In-Memory Computing.
CoRR
Shah Zayed Riam, Zhenlin Pei, Kyle Mooney, Chenyun Pan, Na Gong, Jinhui Wang
2025 J jnl
System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes.
ACM Trans. Embed. Comput. Syst.
Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2025 J jnl
Technology/System Co-Optimization for FPGA Using Emerging Reconfigurable Logic Device.
ACM J. Emerg. Technol. Comput. Syst.
Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Qilian Liang, Chenyun Pan
2024 J jnl
A Low-Noise, Low-Offset CMOS Readout IC for Amperometric Biosensors.
IEEE Access
Manu Chilukuri, Shanthala Lakshminarayana, Hyusim Park, Chenyun Pan, Hoon-Ju Chung, Sungyong Jung
2024 — conf
A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET.
MWSCAS
Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Chenyun Pan
2024 J jnl
Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes.
IEEE Embed. Syst. Lett.
Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2024 — conf
Emerging Reconfigurable Logic Device Based FPGA Design and Optimization.
ISQED
Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan
2024 J jnl
Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsiao-Hsuan Liu, Carlo Gilardi, Shairfe Muhammad Salahuddin, Zhenlin Pei, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert, Chenyun Pan, Subhasish Mitra, Francky Catthoor
2024 J jnl
QPUF 2.0: Exploring Quantum Physical Unclonable Functions for Security-by-Design of Energy Cyber-Physical Systems.
CoRR
Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos
2024 J jnl
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Dawit Burusie Abdi, James Myers, Chenyun Pan
2023 — conf
A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices.
MWSCAS
Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Chenyun Pan
2023 J jnl
A statistical approach for neural network pruning with application to internet of things.
EURASIP J. Wirel. Commun. Netw.
Chengchen Mao, Qilian Liang, Chenyun Pan, Ioannis D. Schizas
2023 J jnl
Deep learning in physical layer communications: Evolution and prospects in 5G and 6G networks.
IET Commun.
Chengchen Mao, Zongwen Mu, Qilian Liang, Ioannis D. Schizas, Chenyun Pan
2023 — conf
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.
ISQED
Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan
2023 — conf
Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis.
MWSCAS
Liuting Shang, Sheng Lu, Sungyong Jung, Chenyun Pan
2023 — conf
QPUF: Quantum Physical Unclonable Functions for Security-by-Design of Industrial Internet-of-Things.
iSES
Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos
2023 — conf
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.
ACM Great Lakes Symposium on VLSI
Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Chenyun Pan
2023 J jnl
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis.
IEEE Open J. Comput. Soc.
Liuting Shang, Azad Naeemi, Chenyun Pan
2020 — conf
Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator.
ISVLSI
Liuting Shang, Muhammad Adil, Ramtin Madani, Chenyun Pan
2019 J jnl
A Mixed Signal Architecture for Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst.
Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu
2018 J jnl
A mixed signal architecture for convolutional neural networks.
CoRR
Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu
2018 — conf
Generic system-level modeling and optimization for beyond CMOS device applications.
ISQED
Victor Huang, Chenyun Pan, Azad Naeemi
2017 J jnl
Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications.
CoRR
Chenyun Pan, Azad Naeemi
2017 A conf
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions.
DATE
Chenyun Pan, Azad Naeemi
2016 J jnl
A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices.
CoRR
Chenyun Pan, Azad Naeemi
2016 — conf
Device/system performance modeling of stacked lateral NWFET logic.
ISQED
Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi
2016 — conf
Impact of interconnect variability on circuit performance in advanced technology nodes.
ISQED
Divya Prasad, Chenyun Pan, Azad Naeemi
2016 — conf
Performance modeling and optimization for on-chip interconnects in 3D memory arrays.
ISQED
Javaneh Mohseni, Chenyun Pan, Azad Naeemi
2015 J jnl
A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chenyun Pan, Azad Naeemi
2015 — conf
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
ISQED
Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi
2014 — conf
An analytical approach to system-level variation analysis and optimization for multi-core processor.
ISQED
Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi
2014 A* conf
BEOL Scaling Limits and Next Generation Technology Prospects.
DAC
Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja
2013 — conf
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs.
ISQED
Chenyun Pan, Ahmet Ceyhan, Azad Naeemi
2012 — conf
Device- and system-level performance modeling for graphene P-N junction logic.
ISQED
Chenyun Pan, Azad Naeemi
2012 — conf
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model.
ICICDT
Chenyun Pan, Azad Naeemi