Chenlei Fang

19 papers A* 4A 5C 2Misc 2Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2023 J jnl
Efficient Test Chip Design via Smart Computation.
ACM Trans. Design Autom. Electr. Syst.
Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton
2021 Misc conf
Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis.
VTS
Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton
2020 — conf
Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors.
ITC-Asia
Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton
2020 — conf
Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest.
ITC-Asia
Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton
2020 A conf
Knowledge Transfer for Diagnosis Outcome Preview with Limited Data.
ITC
Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton
2020 A conf
LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution.
ITC
Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton
2020 J jnl
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer.
ACM Trans. Design Autom. Electr. Syst.
Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. (Shawn) Blanton
2019 Misc conf
Diagnosis Outcome Preview through Learning.
VTS
Chenlei Fang, Qicheng Huang, Soumya Mittal, R. D. Shawn Blanton
2019 C conf
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design.
ICCD
Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton
2019 A conf
Improving Test Chip Design Efficiency via Machine Learning.
ITC
Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton
2018 A conf
Improving Diagnosis Efficiency via Machine Learning.
ITC
Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. Shawn Blanton
2016 J jnl
An aggregating based model order reduction method for power grids.
Integr.
Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng
2016 A* conf
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression.
DAC
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li
2016 A* conf
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits.
DAC
Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li
2016 C conf
High-speed link verification based on statistical inference.
ISCAS
Xuan Zeng, Chenlei Fang, Qicheng Huang, Fan Yang, Dian Zhou, Wei Cai, Weiping Shi
2015 A conf
Efficient bit error rate estimation for high-speed link by Bayesian model fusion.
DATE
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li, Chenjie Gu
2015 A* conf
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits.
DAC
Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li
2015 — conf
PGMOR: An Efficient Model Order Reduction Method for Power Grids.
CAD/Graphics
Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng
2014 A* conf
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits.
DAC
Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li