Chenjia Xie

14 papers C 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations.
IEEE Trans. Very Large Scale Integr. Syst.
Chenjia Xie, Zhuang Shao, Ning Zhao, Xingyuan Hu, Yuan Du, Li Du
2025 — conf
KV Cache Compression Based on Token-Level Redundancy Elimination and Bit-Level Encoding.
AICAS
Tianze Li, Chenjia Xie, Jiayuan Chen, Yuan Du, Li Du
2025 J jnl
RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory.
IEEE J. Solid State Circuits
Chenjia Xie, Zhuang Shao, Mingzhe Zhang, Yuan Du, Li Du
2024 — conf
A Streaming Transformer Accelerator with Efficient On-Chip Normalization.
APCCAS
Ning Zhao, Jiayuan Chen, Jingjing Lv, Chenjia Xie, Yuan Du, Li Du
2024 J jnl
An Efficient GCN Accelerator Based on Workload Reorganization and Feature Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhuang Shao, Chenjia Xie, Zihan Ning, Qi Wu, Liang Chang, Yuan Du, Li Du
2024 — conf
An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling.
APCCAS
Chengrui Li, Ning Zhao, Xiaopeng Zhang, Wei Gao, Chenjia Xie, Yuan Du, Li Du
2024 J jnl
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction.
IEEE Trans. Very Large Scale Integr. Syst.
Chenjia Xie, Zhuang Shao, Zhichao Chen, Yuan Du, Li Du
2023 J jnl
An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chenjia Xie, Zhuang Shao, Ning Zhao, Yuan Du, Li Du
2023 — conf
Graph Neural Network Assisted S-Parameter Inference and Control-Word Generation of Terahertz Reconfigurable Intelligent Surface.
ICTA
Zihan Ning, Tong Sun, Jizhao Li, Yanfei Ren, Chenjia Xie, Li Du, Lianggong Wen, Yuan Du
2023 — conf
Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators.
ASICON
Hang Xu, Chenjia Xie, Xin Lu, Li Du, Yuan Du
2022 C conf
Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting.
ISCAS
Chenjia Xie, Zhuang Shao, Hang Xu, Xiaoliang Chen, Li Du, Yuan Du, Zhongfeng Wang
2022 J jnl
Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang
2022 — conf
SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access.
ISOCC
Xingyuan Hu, Zhuang Shao, Chenjia Xie, Li Du, Yuan Du
2021 J jnl
Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression.
CoRR
Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang