Chengshuo Yu

21 papers C 4Journal 9Unranked 8
YearRankTypeTitle / Venue / Authors
2025 C conf
A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit.
ISCAS
Honghu Yang, Yongkang Han, Tianci Cai, Chengshuo Yu, Keji Zhou, Jianguo Yang
2025 C conf
A High-Density RRAM-Based Ising Machine with Analog In-Memory Operation for Solving Combinatorial Optimization Problems.
ISCAS
Jingxin Deng, Keji Zhou, Honghu Yang, Chengshuo Yu, Jianguo Yang
2025 C conf
A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme.
ISCAS
Yue Cao, Yuanyuan Han, Keji Zhou, Chengshuo Yu, Tianci Cai, Jianguo Yang
2025 J jnl
Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yixuan Liu, Qiqiao Wu, Honghu Yang, Chengshuo Yu, Keji Zhou, Yu Jiang, Haijun Jiang, Hailan Yi, Xiaoyong Xue, Jianguo Yang, Xiaoyang Zeng
2024 J jnl
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chengshuo Yu, Haoge Jiang, Junjie Mu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2024 J jnl
A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations.
IEEE J. Solid State Circuits
Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2024 J jnl
CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States.
IEEE J. Solid State Circuits
Jooyoung Bae, Wonsik Oh, Jahyun Koo, Chengshuo Yu, Bongjin Kim
2023 C conf
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
ISCAS
Qibang Zang, Wang Ling Goh, Lu Lu, Chengshuo Yu, Junjie Mu, Tony Tae-Hyoung Kim, Bongjin Kim, Dongrui Li, Anh Tuan Do
2023 J jnl
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hyunjoon Kim, Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2023 — conf
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations.
VLSI Technology and Circuits
Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2023 — conf
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates.
CICC
Chengshuo Yu, Junjie Mu, Kevin Tshun-Chuan Chai, Tony T. Kim, Bongjin Kim
2023 J jnl
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
IEEE J. Solid State Circuits
Chengshuo Yu, Junjie Mu, Yuqi Su, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2022 J jnl
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.
IEEE J. Solid State Circuits
Chengshuo Yu, Taegeun Yoo, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2022 — conf
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method.
ESSCIRC
Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2022 J jnl
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep P. Kulkarni, Tony Tae-Hyoung Kim
2021 — conf
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations.
CICC
Chengshuo Yu, Yuqi Su, Jaeho Lee, Kevin T. C. Chai, Bongjin Kim
2021 J jnl
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chengshuo Yu, Taegeun Yoo, Hyunjoon Kim, Tony Tae-Hyoung Kim, Kevin Chai Tshun Chuan, Bongjin Kim
2021 — conf
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
ESSCIRC
Chengshuo Yu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2021 — conf
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
ESSDERC
Chengshuo Yu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2020 — conf
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
CICC
Chengshuo Yu, Taegeun Yoo, Tony Tae-Hyoung Kim, Kevin Tshun Chuan Chai, Bongjin Kim
2020 — conf
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks.
ISOCC
Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan