Chenggang Yan

29 papers A* 1C 5Journal 15Unranked 8
YearRankTypeTitle / Venue / Authors
2026 — conf
BIHDC: A Retrainable Fully-Binary Hyperdimensional Computing Accelerator for Edge FPGAs.
ASP-DAC
Changzhen Han, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu
2025 J jnl
HDANNS: In-Memory Hyperdimensional Computing for Billion-Scale Approximate Nearest Neighbour Search Acceleration.
IEEE Trans. Circuits Syst. Artif. Intell.
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Gong Zhang, Weiqiang Liu
2025 A* conf
PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing.
DAC
Ziying Cui, Ke Chen, Bi Wu, Yu Gong, Chenggang Yan, Weiqiang Liu
2025 J jnl
SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Yang Hu, Shuo Ran, Xun Zhang, Ke Chen, Chenggang Yan, Weiqiang Liu
2024 J jnl
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Haonan Zhu, Bi Wu, Tianyang Yu, Ke Chen, Chenggang Yan, Weiqiang Liu
2024 C conf
A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration.
ARITH
Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Yu Gong, Weiqiang Liu
2024 J jnl
Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu
2023 — conf
A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.
MWSCAS
Wenzhuo Xie, Chenggang Yan, Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu
2023 J jnl
Design of High Hardware Efficiency Approximate Floating-Point FFT Processor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chenggang Yan, Xuan Zhao, Tingting Zhang, Jipeng Ge, Chenghua Wang, Weiqiang Liu
2023 J jnl
Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chenggang Yan, Yuxuan Cui, Ke Chen, Bi Wu, Weiqiang Liu
2023 — conf
Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.
MWSCAS
Haonan Wang, Ke Chen, Chenggang Yan, Bi Wu, Weiqiang Liu
2023 C conf
High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes.
ISCAS
Yuxuan Cui, Chenggang Yan, Weiqiang Liu
2023 J jnl
MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Haonan Zhu, Ke Chen, Chenggang Yan, Weiqiang Liu
2022 — conf
An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications.
APCCAS
Jipeng Ge, Chenggang Yan, Xuan Zhao, Ke Chen, Bi Wu, Weiqiang Liu
2022 — conf
An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits.
ACM Great Lakes Symposium on VLSI
Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu
2022 — conf
Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy.
ACM Great Lakes Symposium on VLSI
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu
2022 — conf
Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm.
APCCAS
Xuan Zhao, Chenggang Yan, Chenghua Wang, Weiqiang Liu
2022 C conf
Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration.
ICCD
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu
2022 J jnl
GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Zhengkuan Wang, Ke Chen, Chenggang Yan, Weiqiang Liu
2021 C conf
A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function.
ISCAS
Hu Zhang, Chenghua Wang, Chenggang Yan, Yijun Cui, Chongyan Gu, Máire O'Neill, Weiqiang Liu
2021 J jnl
An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering.
IEEE Trans. Very Large Scale Integr. Syst.
Chenggang Yan, Jie Sun, Weiqiang Liu
2021 J jnl
Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows.
IEEE Trans. Circuits Syst. II Express Briefs
Jie Sun, Xin Ding, Chenggang Yan, Weiqiang Liu
2021 — conf
Design of An Approximate FFT Processor Based on Approximate Complex Multipliers.
ISVLSI
Jinhe Du, Ke Chen, Peipei Yin, Chenggang Yan, Weiqiang Liu
2020 J jnl
A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator.
IEEE Trans. Circuits Syst. II Express Briefs
Chenggang Yan, Jianhui Wu, Jie Sun, Jin Jin, Chen Hu
2020 J jnl
A Low-Spur MASH Delta-Sigma Modulator With an Adaptive Length Extension Technique.
IEEE Trans. Circuits Syst.
Xin Ding, Chenggang Yan, Xin Li, Jianhui Wu
2020 C conf
Active Noise Shaping SAR ADC Based on ISDM with the 5MHz Bandwidth.
ISCAS
Bo Gao, Xin Li, Chenggang Yan, Jianhui Wu
2019 J jnl
A digital-mixing-based method for timing skew estimation in time-interleaved ADCs.
Microelectron. J.
Xin Li, Desheng Ding, Chenggang Yan, Jianhui Wu
2019 J jnl
A low power wide tuning range two stage ring VCO with frequency enhancing.
IEICE Electron. Express
Chenggang Yan, Jianhui Wu, Chen Hu, Xincun Ji
2018 J jnl
A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control.
J. Circuits Syst. Comput.
Chenggang Yan, Chen Hu