Cheng-Wen Wu - RankMe

256 papers A* 7A 29B 7C 3Misc 23Journal 91Unranked 96

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Chiplet Interconnect Test and Repair. ITC Po-Yao Chuang, Cheng-Wen Wu, Erik Jan Marinissen
2025	J	`jnl`	Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Po-Yao Chuang, Francesco Lorenzelli, Cheng-Wen Wu, Erik Jan Marinissen
2024	B	`conf`	Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. ETS Cheng-Wen Wu, Shi-Yu Huang
2023	J	`jnl`	A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation. IEEE Trans. Very Large Scale Integr. Syst. Pai-Yu Tan, Cheng-Wen Wu
2023	—	`conf`	A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks. ASP-DAC Pai-Yu Tan, Cheng-Wen Wu
2023	—	`conf`	Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2023	Misc	`conf`	Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2022	—	`conf`	A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips. ITC-Asia Ya-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao
2022	—	`conf`	A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. VLSI-DAT Pai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao
2022	—	`conf`	A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime. VLSI-DAT Hong-Hao Wang, Po-Yao Chuang, Cheng-Wen Wu
2022	—	`conf`	Aging Impact of Power MOSFETs in Charger with Different Operation Frequency. ATS Kuan-Hsun Duh, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen, Ming-Yan Fan
2022	—	`conf`	Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration. ATS Yu-You Chou, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen
2022	J	`jnl`	Enhancing Fan Engagement in a 5G Stadium With AI-Based Technologies and Live Streaming. IEEE Syst. J. Cheng-Wen Wu, Ming-Der Shieh, Jenn-Jier James Lien, Jar-Ferr Yang, Wei-Ta Chu, Tsang-Hai Huang, Han-Chuan Hsieh, Hung-Ta Chiu, Kuo-Cheng Tu, Yen-Ting Chen, Shian-Yu Lin, Jia-Jun Hu, Chen-Huan Lin, Cheng-Siang Jheng
2022	A	`conf`	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks. ITC Kuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu, Juin-Ming Lu
2022	J	`jnl`	Impact Position Estimation for Baseball Batting with a Force-Irrelevant Vibration Feature. Sensors Wei-Han Chen, Yang-Chih Feng, Ming-Chia Yeh, Hsi-Pin Ma, Chiang Liu, Cheng-Wen Wu
2022	A	`conf`	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method. ITC Ya-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao
2022	—	`conf`	Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability. ITC-Asia Shian-Yu Lin, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao
2021	A	`conf`	An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. DATE Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu
2021	J	`jnl`	Automated Probe-Mark Analysis for Advanced Probe Technology Characterization. IEEE Des. Test Yu-Rong Jian, Ferenc Fodor, Cheng-Wen Wu, Erik Jan Marinissen
2020	A*	`conf`	A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. DAC Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu
2020	—	`conf`	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2020	A	`conf`	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2020	J	`jnl`	A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. CoRR Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu
2020	B	`conf`	Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. ETS Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen
2019	A	`conf`	Asian Test Symposium - Past, Present and Future -. ITC Michiko Inoue, Xiaowei Li, Cheng-Wen Wu
2019	J	`jnl`	The Last Byte: Baseball and Testing. IEEE Des. Test Cheng-Wen Wu
2018	—	`conf`	A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit. ATS Meng-Chi Chen, Tsung-Hsuan Wu, Cheng-Wen Wu
2018	Misc	`conf`	A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning. ACSSC Ying-Cih Kao, Cheng-Wen Wu
2018	B	`conf`	Covering hard-to-detect defects by thermal quorum sensing. ETS Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen
2018	—	`conf`	RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. ITC-Asia Jia-Yun Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu
2018	A	`conf`	Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu
2018	—	`conf`	Symbiotic Controller Design Using a Memory-Based FSM Model. ISIE Su-Fu Kuo, Cheng-Wen Wu
2017	J	`jnl`	A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2017	—	`conf`	An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. ATS Pok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong
2017	—	`conf`	Can IOT make semiconductor great again? VLSI-DAT Cheng-Wen Wu
2017	—	`conf`	Cell-aware test generation time reduction by using switch-level ATPG. ITC-Asia Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen
2017	J	`jnl`	Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. IEEE Des. Test Zhi-Yong Liu, Hsiu-Chuan Shih, Bing-Yang Lin, Cheng-Wen Wu
2017	A	`conf`	Highly reliable and low-cost symbiotic IOT devices and systems. ITC Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu
2017	—	`conf`	Symbiotic system models for efficient IGT system design and test. ITC-Asia Cheng-Wen Wu, Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen
2017	J	`jnl`	Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	J	`jnl`	A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	B	`conf`	A fast sweep-line-based failure pattern extractor for memory diagnosis. ETS Sin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu
2016	J	`jnl`	Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	—	`conf`	Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. ATS Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu
2016	A*	`conf`	Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	B	`conf`	Is IoT coming to the rescue of semiconductor? ETS Cheng-Wen Wu
2016	—	`conf`	Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. ATS Hsuan-Wei Liu, Bing-Yang Lin, Cheng-Wen Wu
2015	—	`conf`	A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu
2015	—	`conf`	System-level test coverage prediction by structural stress test data mining. VLSI-DAT Bing-Yang Lin, Cheng-Wen Wu, Harry H. Chen
2015	J	`jnl`	YM500v2: a small RNA sequencing (smRNA-seq) database for human cancer miRNome research. Nucleic Acids Res. Wei-Chung Cheng, I-Fang Chung, Cheng-Fong Tsai, Tse-Shun Huang, Chen-Yang Chen, Shao-Chuan Wang, Ting-Yu Chang, Hsing-Jen Sun, Jeffrey Yung-Chuan Chao, Cheng-Chung Cheng, Cheng-Wen Wu, Hsei-Wei Wang
2014	J	`jnl`	Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. IEEE Trans. Very Large Scale Integr. Syst. Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2014	—	`conf`	BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2014	J	`jnl`	DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
2014	J	`jnl`	Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2014	J	`jnl`	On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng
2014	A	`conf`	Redundancy architectures for channel-based 3D DRAM yield improvement. ITC Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2013	Misc	`conf`	3D-IC interconnect test, diagnosis, and repair. VTS Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin
2013	—	`conf`	A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013	Misc	`conf`	A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013	J	`jnl`	AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
2013	—	`conf`	An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013	A	`conf`	An enhanced double-TSV scheme for defect tolerance in 3D-IC. DATE Hsiu-Chuan Shih, Cheng-Wen Wu
2013	—	`conf`	Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs. ISQED Yuriy Shiyanovskii, Christos A. Papachristou, Cheng-Wen Wu
2013	—	`conf`	Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
2013	J	`jnl`	Generalization of an Enhanced ECC Methodology for Low Power PSRAM. IEEE Trans. Computers Po-Yuan Chen, Chin-Lung Su, Chao-Hsun Chen, Cheng-Wen Wu
2013	A	`conf`	Holistic approach to low-power system design. ISLPED Cheng-Wen Wu
2013	J	`jnl`	In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013	J	`jnl`	Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu
2013	—	`conf`	Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. ASP-DAC Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu
2013	J	`jnl`	Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. IEEE Trans. Circuits Syst. I Regul. Pap. Yung-Fa Chou, Ding-Ming Kwai, Ming-Der Shieh, Cheng-Wen Wu
2013	Misc	`conf`	Special session 4C: Hot topic 3D-IC design and test. VTS Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai
2013	J	`jnl`	Write Current Self-Configuration Scheme for MRAM Yield Improvement. IEEE Trans. Very Large Scale Integr. Syst. Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu
2012	—	`conf`	3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin
2012	Misc	`conf`	A Memory Failure Pattern Analyzer for memory diagnosis and repair. VTS Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
2012	A	`conf`	A built-in self-test scheme for 3D RAMs. ITC Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2012	A	`conf`	A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang
2012	Misc	`conf`	Cost modeling and analysis for interposer-based three-dimensional IC. VTS Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu
2012	—	`conf`	On test and repair of 3D random access memory. ASP-DAC Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li
2011	J	`jnl`	A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. IEEE Trans. Very Large Scale Integr. Syst. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu
2011	J	`jnl`	A Memory Built-In Self-Repair Scheme Based on Configurable Spares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mincent Lee, Li-Ming Denq, Cheng-Wen Wu
2011	Misc	`conf`	A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2011	A*	`conf`	A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
2011	—	`conf`	A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
2011	B	`conf`	DfT Architecture for 3D-SICs with Multiple Towers. ETS Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	—	`conf`	Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	A	`conf`	Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	Misc	`conf`	Special session: Hot topic design and test of 3D and emerging memories. VTS Cheng-Wen Wu
2011	Misc	`conf`	Training-based forming process for RRAM yield improvement. VTS Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu
2011	J	`jnl`	Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu
2010	J	`jnl`	A Mesh-Structured Scalable IPsec Processor. IEEE Trans. Very Large Scale Integr. Syst. Mao-Yin Wang, Cheng-Wen Wu
2010	—	`conf`	A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2010	B	`conf`	A low-cost and scalable test architecture for multi-core chips. ETS Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li
2010	—	`conf`	AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
2010	J	`jnl`	An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. Chen-Hsing Wang, Chieh-Lin Chuang, Cheng-Wen Wu
2010	A	`conf`	An adaptive code rate EDAC scheme for random access memory. DATE Ching-Yi Chen, Cheng-Wen Wu
2010	A*	`conf`	An error tolerance scheme for 3D CMOS imagers. DAC Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu
2010	J	`jnl`	Built-In Self-Repair Schemes for Flash Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
2010	J	`jnl`	Diagnosis of MRAM Write Disturbance Fault. IEEE Trans. Very Large Scale Integr. Syst. Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2010	J	`jnl`	Economic Analysis of the HOY Wireless Test Methodology. IEEE Des. Test Comput. Yu-Tsao Hsing, Li-Ming Denq, Chao-Hsun Chen, Cheng-Wen Wu
2010	J	`jnl`	Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu
2010	A*	`conf`	Fast identification of operating current for toggle MRAM by spiral search. DAC Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu
2010	—	`conf`	Is 3D integration an opportunity or just a hype? ASP-DAC Jin-Fu Li, Cheng-Wen Wu
2010	Misc	`conf`	On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. VTS Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai
2010	—	`conf`	Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2010	J	`jnl`	SOC Test Architecture and Method for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Denq, Cheng-Wen Wu
2010	J	`jnl`	Single- and Multi-core Configurable AES Architectures for Flexible Security. IEEE Trans. Very Large Scale Integr. Syst. Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu, Chih-Tsun Huang
2009	Misc	`conf`	An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. VTS Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu
2009	J	`jnl`	Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. IEEE Des. Test Comput. Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu
2009	—	`conf`	On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. Asian Test Symposium Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai
2009	—	`conf`	Test Integration for SOC Supporting Very Low-Cost Testers. Asian Test Symposium Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu
2008	J	`jnl`	A Systematic Approach to Memory Test Time Reduction. IEEE Des. Test Comput. Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo
2008	—	`conf`	Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. ATS Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
2008	—	`conf`	Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault. ATS Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, Cheng-Wen Wu
2008	J	`jnl`	Write Disturbance Modeling and Testing for MRAM. IEEE Trans. Very Large Scale Integr. Syst. Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang, Yuan-Jen Lee, Ming-Jer Kao
2007	—	`conf`	A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. ATS Li-Ming Denq, Cheng-Wen Wu
2007	—	`conf`	A prototype of a wireless-based test system. SoCC Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang
2007	J	`jnl`	BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. IET Comput. Digit. Tech. Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang
2007	—	`conf`	CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. ATS Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu
2007	A	`conf`	Diagnosis for MRAM write disturbance fault. ITC Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2007	J	`jnl`	Economic Aspects of Memory Built-in Self-Repair. IEEE Des. Test Comput. Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu
2007	J	`jnl`	Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
2007	J	`jnl`	Raisin: Redundancy Analysis Algorithm Simulation. IEEE Des. Test Comput. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2007	Misc	`conf`	SDRAM Delay Fault Modeling and Performance Testing. VTS Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu
2007	J	`jnl`	SOC Testing Methodology and Practice CoRR Cheng-Wen Wu
2007	J	`jnl`	STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
2007	—	`conf`	Test Education in the Global Economy. ATS Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu
2006	Misc	`conf`	A Built-In Self-Repair Scheme for NOR-Type Flash Memory. VTS Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
2006	A*	`conf`	A network security processor design based on an integrated SOC design and test platform. DAC Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
2006	A	`conf`	An Enhanced EDAC Methodology for Low Power PSRAM. ITC Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin
2006	—	`conf`	An Enhanced SRAM BISR Design with Reduced Timing Penalty. ATS Li-Ming Denq, Tzu-chiang Wang, Cheng-Wen Wu
2006	J	`jnl`	Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
2006	—	`conf`	Fault-Pattern Oriented Defect Diagnosis for Flash Memory. MTDT Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu
2006	Misc	`conf`	Session Abstract. VTS Cheng-Wen Wu
2006	A	`conf`	Testing MRAM for Write Disturbance Fault. ITC Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao
2005	Misc	`conf`	A BIST Scheme for FPGA Interconnect Delay Faults. VTS Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
2005	J	`jnl`	A built-in self-repair design for RAMs with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
2005	—	`conf`	A configurable AES processor for enhanced security. ASP-DAC Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
2005	—	`conf`	A systematic approach to reducing semiconductor memory test time in mass production. MTDT Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen
2005	—	`conf`	An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. DFT Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu
2005	—	`conf`	Design and test of a scalable security processor. ASP-DAC Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2005	Misc	`conf`	Flash Memory Built-In Self-Diagnosis with Test Mode Control. VTS Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin
2005	—	`conf`	Flash Memory Die Sort by a Sample Classification Method. Asian Test Symposium Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen
2005	A	`conf`	SOC Testing Methodology and Practice. DATE Cheng-Wen Wu
2004	J	`jnl`	A Graph-Based Approach to Power-Constrained SOC Test Scheduling. J. Electron. Test. Chih-Pin Su, Cheng-Wen Wu
2004	—	`conf`	A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. MTDT Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
2004	—	`conf`	A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. Asian Test Symposium Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng
2004	—	`conf`	An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
2004	—	`conf`	An HMAC processor with integrated SHA-1 and MD5 algorithms. ASP-DAC Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
2004	J	`jnl`	Efficient and Economical Test Equipment Setup Using Procorrelation. IEEE Des. Test Comput. Bin-Hong Lin, Cheng-Wen Wu, Hwei-Tsu Ann Luh
2004	—	`conf`	Fail Pattern Identification for Memory Built-In Self-Repair. Asian Test Symposium Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang
2004	—	`conf`	Failure Factor Based Yield Enhancement for SRAM Designs. DFT Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu
2004	A	`conf`	MRAM Defect Analysis and Fault Modeli. ITC Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
2004	—	`conf`	On Test and Diagnostics of Flash Memories. Asian Test Symposium Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu
2004	—	`conf`	SRAM delay fault modeling and test algorithm development. ASP-DAC Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu
2003	A	`conf`	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ITC Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow
2003	—	`conf`	A Processor-Based Built-In Self-Repair Design for Embedded Memories. Asian Test Symposium Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
2003	—	`conf`	A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. MTDT Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
2003	J	`jnl`	A high-throughput low-cost AES processor. IEEE Commun. Mag. Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
2003	—	`conf`	A highly efficient AES cipher chip. ASP-DAC Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
2003	J	`jnl`	Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition. J. Inf. Sci. Eng. Shao-Hui Shieh, Cheng-Wen Wu
2003	J	`jnl`	Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
2003	J	`jnl`	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. IEEE Trans. Very Large Scale Integr. Syst. Jin-Hua Hong, Cheng-Wen Wu
2003	—	`conf`	Combinational circuit fault diagnosis using logic emulation. ISCAS (5) Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang
2003	—	`conf`	Defect Oriented Fault Analysis for SRAM. Asian Test Symposium Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu
2003	—	`conf`	Design of a scalable RSA and ECC crypto-processor. ASP-DAC Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
2003	J	`jnl`	Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu
2003	A	`conf`	FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2003	A	`conf`	Fault Pattern Oriented Defect Diagnosis for Memories. ITC Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
2003	J	`jnl`	Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai
2003	Misc	`conf`	Test and Diagnosis of Word-Oriented Multiport Memories. VTS Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2003	J	`jnl`	Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. J. Electron. Test. Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
2002	J	`jnl`	A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electron. Test. Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
2002	J	`jnl`	A Hierarchical Test Methodology for Systems on Chip. IEEE Micro Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
2002	A	`conf`	A Hierarchical Test Scheme for System-On-Chip Designs. DATE Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
2002	—	`conf`	A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. IOLTW Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2002	—	`conf`	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. MTDT Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2002	J	`jnl`	Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. J. Electron. Test. Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
2002	A	`conf`	Diagonal Test and Diagnostic Schemes for Flash Memorie. ITC Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2002	J	`jnl`	Efficient FFT network testing and diagnosis schemes. IEEE Trans. Very Large Scale Integr. Syst. Jin-Fu Li, Cheng-Wen Wu
2002	J	`jnl`	Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
2002	—	`conf`	Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2002	J	`jnl`	Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
2002	—	`conf`	On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu
2002	Misc	`conf`	RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
2002	—	`conf`	Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2002	—	`conf`	Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2002	Misc	`conf`	Testing and Diagnosing Embedded Content Addressable Memories. VTS Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
2001	—	`conf`	A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
2001	—	`conf`	A Profit Evaluation System (PES) for logic cores at early design stage. ICECS Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
2001	—	`conf`	Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2001	Misc	`conf`	Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. VTS Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
2001	A	`conf`	March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2001	A	`conf`	Memory fault diagnosis by syndrome compression. DATE Jin-Fu Li, Cheng-Wen Wu
2001	—	`conf`	Processor-programmable memory BIST for bus-connected embedded memories. ASP-DAC Ching-Hong Tsai, Cheng-Wen Wu
2001	—	`conf`	RSA cryptosystem design based on the Chinese remainder theorem. ASP-DAC Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu
2001	A*	`conf`	Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
2001	J	`jnl`	Unified VLSI systolic array design for LZ data compression. IEEE Trans. Very Large Scale Integr. Syst. Shih-Arn Hwang, Cheng-Wen Wu
2001	J	`jnl`	VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem. J. Inf. Sci. Eng. Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu
2000	J	`jnl`	A Low-Power CAM Design for LZ Data Compression. IEEE Trans. Computers Kun-Jin Lin, Cheng-Wen Wu
2000	J	`jnl`	A Probabilistic Model for Path Delay Fault Testing. J. Inf. Sci. Eng. Chih-Yuang Su, Cheng-Wen Wu
2000	—	`conf`	A Testable/Fault Tolerant FFT Processor Design. Asian Test Symposium Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu
2000	—	`conf`	A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
2000	J	`jnl`	A fast signature computation algorithm for LFSR and MISR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
2000	—	`conf`	A programmable built-in self-test core for embedded memories. ASP-DAC Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
2000	—	`conf`	A waveform simulator based on Boolean process. Asian Test Symposium Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Yinghua Min
2000	—	`conf`	An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu
2000	—	`conf`	BRAINS: A BIST Compiler for Embedded Memories. DFT Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai
2000	C	`conf`	Built-in self-test and fault diagnosis for lookup table FPGAs. ISCAS Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu
2000	A	`conf`	Cost and Benefit Models for Logic and Memory BIST. DATE Juin-Ming Lu, Cheng-Wen Wu
2000	A	`conf`	Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
2000	J	`jnl`	Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core. IEEE Trans. Very Large Scale Integr. Syst. Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu
2000	—	`conf`	Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. ASP-DAC Jin-Hua Hong, Cheng-Wen Wu
2000	Misc	`conf`	Simulation-Based Test Algorithm Generation for Random Access Memories. VTS Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
2000	J	`jnl`	Testing and Diagnosing Dynamic Reconfigurable FPGA. VLSI Design Chi-Feng Wu, Cheng-Wen Wu
2000	J	`jnl`	Testing content-addressable memories using functional fault modelsand march-like algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kun-Jin Lin, Cheng-Wen Wu
1999	J	`jnl`	A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
1999	—	`conf`	A novel approach to testing LUT-based FPGAs. ISCAS (1) Shyue-Kung Lu, Cheng-Wen Wu
1999	J	`jnl`	An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem. IEEE Trans. Very Large Scale Integr. Syst. Chih-Yuang Su, Shih-Am Hwang, Po-Song Chen, Cheng-Wen Wu
1999	—	`conf`	Defect Level Prediction Using Multi-Model Fault Coverage. Asian Test Symposium Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
1999	J	`jnl`	Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code. IEEE Trans. Computers Wen-Feng Chang, Cheng-Wen Wu
1999	—	`conf`	RAMSES: A Fast Memory Fault Simulator. DFT Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
1999	J	`jnl`	TSC Berger-Code Checker Design for 2r-1-Bit Information. J. Inf. Sci. Eng. Wen-Feng Chang, Cheng-Wen Wu
1999	J	`jnl`	Test Energy Minimization for C-Testable ILAs. J. Inf. Sci. Eng. Shih-Arn Hwang, Cheng-Wen Wu
1999	—	`conf`	Testable and Fault Tolerant Design for FFT Networks. DFT Jin-Fu Li, Cheng-Wen Wu
1999	—	`conf`	Testing Interconnects of Dynamic Reconfigurable FPGAs. ASP-DAC Chi-Feng Wu, Cheng-Wen Wu
1998	—	`conf`	A Probabilistic Model for Path Delay Faults. Asian Test Symposium Cheng-Wen Wu, Chih-Yuang Su
1998	J	`jnl`	Control and Observation Structures for Analog Circuits. IEEE Des. Test Comput. Yeong-Ruey Shieh, Cheng-Wen Wu
1998	J	`jnl`	Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults. VLSI Design Yeong-Ruey Shieh, Cheng-Wen Wu
1998	—	`conf`	On-Line Error Detection Schemes for a Systolic Finite-Field Inverter. Asian Test Symposium Yu-Chun Chuang, Cheng-Wen Wu
1998	J	`jnl`	Sequential circuit fault simulation using logic emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu
1998	—	`conf`	Testing Embedded Memories: Is BIST the Ultimate Solution? Asian Test Symposium Cheng-Wen Wu
1997	J	`jnl`	Does There Exist a Combinational TSC Checker for 1/3 Code Using Only Primitive Gates? J. Inf. Sci. Eng. Wen-Feng Chang, Cheng-Wen Wu
1997	J	`jnl`	Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy. IEEE Trans. Computers Shyue-Kung Lu, Sy-Yen Kuo, Cheng-Wen Wu
1997	—	`conf`	High-speed C-testable systolic array design for Galois-field inversion. ED&TC Chih-Tsun Huang, Cheng-Wen Wu
1997	—	`conf`	On energy efficiency of VLSI testing. Asian Test Symposium Cheng-Wen Wu
1997	J	`jnl`	Practical Realization of Multiple-Input Exclusive-OR Circuits for Low-Power Applications. J. Circuits Syst. Comput. Kun-Jin Lin, Cheng-Wen Wu
1996	—	`conf`	A MISR Computation Algorithm for Fast Signature Simulation. Asian Test Symposium Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
1996	J	`jnl`	Cell delay fault testing for iterative logic arrays. J. Electron. Test. Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang
1996	—	`conf`	Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. Asian Test Symposium Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu
1995	J	`jnl`	Bit-level systolic arrays for finite-field multiplications. J. VLSI Signal Process. Cheng-Wen Wu, Ming-Kwang Chang
1995	J	`jnl`	C-testable design techniques for iterative logic arrays. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu
1995	J	`jnl`	Cellular automata for efficient parallel logic and fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yih-Lang Li, Cheng-Wen Wu
1995	—	`conf`	DC control and observation structures for analog circuits. Asian Test Symposium Yeong-Ruey Shieh, Cheng-Wen Wu
1994	C	`conf`	General Modular Multiplication by Block Multiplication and Table Lookup. ISCAS Cheng-Wen Wu, Yung-Fa Chou
1994	—	`conf`	Logic and Fault Simulation by Cellular Automata. EDAC-ETC-EUROASIC Yih-Lang Li, Cheng-Wen Wu
1994	J	`jnl`	Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. IEEE Trans. Computers Shih-Yuang Su, Cheng-Wen Wu
1993	J	`jnl`	Fault-Tolerant FFT Butterfly Network Design. J. Inf. Sci. Eng. Cheng-Wen Wu, Jiann-Yuan Choue
1991	J	`jnl`	Bit-level pipelined 2-D digital filters for real-time image processing. IEEE Trans. Circuits Syst. Video Technol. Cheng-Wen Wu
1991	C	`conf`	Designing Self-Testable Cellular Arrays. ICCD Cheng-Wen Wu, Shyue-Kung Lu
1991	J	`jnl`	Easily Testable Cellular Array Multipliers. J. Inf. Sci. Eng. Kun-Jin Lin, Cheng-Wen Wu
1990	J	`jnl`	Easily Testable Iterative Logic Arrays. IEEE Trans. Computers Cheng-Wen Wu, Peter R. Cappello
1990	J	`jnl`	Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays. J. Inf. Sci. Eng. Cheng-Wen Wu
1988	J	`jnl`	Application-specific CAD of VLSI second-order sections. IEEE Trans. Acoust. Speech Signal Process. Cheng-Wen Wu, Peter R. Cappello
1987	—	`conf`	Application-Specific CAD of High-Throughout IIR Filters. COMPCON Cheng-Wen Wu, Peter R. Cappello
1987	J	`jnl`	Computer-aided design of VLSI FIR filters. Proc. IEEE Peter R. Cappello, Cheng-Wen Wu
1987	Misc	`conf`	Computer-aided design of VLSI second-order sections. ICASSP Cheng-Wen Wu, Peter R. Cappello