Cheng-Ru Ho - RankMe

13 papers Journal 4Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET. ISSCC J. Q. Wang, Amber Tan, Amrutha Iyer, A. Fan, A. Farhoodfar, B. Alnabulsi, B. Smith, Chang-Feng Loi, Cheng-Ru Ho, D. Cartina, Jamal Riani, J. Casanova, Karthik Raviprakash, Lokanath Patra, Luke Wang, M. Bachu, Sagar Ray, Sau Siong Chong, S. Dallaire, The Linh Nguyen, Tzu-Fan Wu, Vishal Giridharan, V. Gurumoorthy, X. Ding, Y. Yin, Zhuochao Sun, Steve Jantzi, Lawrence Tse
2023	—	`conf`	A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers. OFC Arik Zafrany, Daniel Burgos, Li Cai, Sau Siong Chong, Colin Cramm, Sadegh Dadash, Vishal Giridharan, Vivek Gurumoorthy, Belal Helal, Cheng-Ru Ho, Amrutha Iyer, Steve Jantzi, Chang-Feng Loi, The Linh Nguyen, Kevin Parker, Ed Pillai, Karthik Raviprakash, Sagar Ray, Paolo Rossi, Zhuochao Sun, Amber Tan, Lawrence Tse, Brian Wall, Luke Wang, Jeffrey Wang, Tzu-Fan Wu
2022	J	`jnl`	A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2021	—	`conf`	29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2021	—	`conf`	8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET. ISSCC P. Mishra, Amber Tan, Belal Helal, Cheng-Ru Ho, C. Loi, Jamal Riani, J. Sun, Kaizad Mistry, Karthik Raviprakash, L. Tse, Mehdi Davoodi, M. Takefman, N. Fan, P. Prabha, Q. Liu, Q. Wang, Rajasekhar Nagulapalli, S. Cyrusian, S. Jantzi, S. Scouten, T. Dusatko, T. Setya, V. Giridharan, V. Gurumoorthy, Victor Karam, W. Liew, Y. Liao, Y. Ou
2018	—	`conf`	A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. ISSCC Cheng-Ru Ho, Mike Shuo-Wei Chen
2018	—	`conf`	A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ISSCC Cheng-Ru Ho, Mike Shuo-Wei Chen
2017	J	`jnl`	A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter. IEEE J. Solid State Circuits Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen
2016	—	`conf`	10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. ISSCC Cheng-Ru Ho, Mike Shuo-Wei Chen
2016	J	`jnl`	A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. IEEE J. Solid State Circuits Cheng-Ru Ho, Mike Shuo-Wei Chen
2016	J	`jnl`	A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Cheng-Ru Ho, Mike Shuo-Wei Chen
2016	—	`conf`	Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. ESSCIRC Cheng-Ru Ho, Mike Shuo-Wei Chen
2015	—	`conf`	A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. CICC Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen