Cheng-Kok Koh - RankMe

160 papers A* 10A 35C 10Journal 47Unranked 54

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Full-Scale GPU-Accelerated Transient EM-Thermal-Mechanical Co-Simulation for Early-Stage Design of Advanced Packages. CoRR Hongyang Liu, Tejas Kulkarni, Ganesh Subbarayan, Cheng-Kok Koh, Dan Jiao
2025	J	`jnl`	Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seunghyun Hwang, Michael Joseph Smith, Vinicius C. Do Nascimento, Qiang Qiu, Cheng-Kok Koh, Ganesh Subbarayan, Dan Jiao
2022	J	`jnl`	A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Supriyo Maji, Cheng-Kok Koh
2021	J	`jnl`	A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Supriyo Maji, Cheng-Kok Koh
2021	J	`jnl`	Saath: Speeding up CoFlows by Exploiting the Spatial Dimension. CoRR Akshay Jajoo, Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh
2019	J	`jnl`	Scalable Construction of Clock Trees With Useful Skew and High Timing Quality. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rickard Ewetz, Cheng-Kok Koh
2018	—	`conf`	Clustering of flip-flops for useful-skew clock tree synthesis. ASP-DAC Chuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh
2017	—	`conf`	Clock Tree Construction based on Arrival Time Constraints. ISPD Rickard Ewetz, Cheng-Kok Koh
2017	—	`conf`	Delay-driven layer assignment for advanced technology nodes. ASP-DAC Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang
2017	J	`jnl`	Fast clock scheduling and an application to clock tree synthesis. Integr. Rickard Ewetz, Cheng-Kok Koh
2017	A	`conf`	Saath: Speeding up CoFlows by Exploiting the Spatial Dimension. CoNEXT Akshay Jajoo, Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh
2016	J	`jnl`	An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks. IEEE Trans. Syst. Man Cybern. Syst. Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee
2016	—	`conf`	Construction of Latency-Bounded Clock Trees. ISPD Rickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh
2016	J	`jnl`	Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression. ACM Trans. Design Autom. Electr. Syst. Rickard Ewetz, Cheng-Kok Koh
2016	—	`conf`	MCMM clock tree optimization based on slack redistribution using a reduced slack graph. ASP-DAC Rickard Ewetz, Cheng-Kok Koh
2015	—	`conf`	A Useful Skew Tree Framework for Inserting Large Safety Margins. ISPD Rickard Ewetz, Cheng-Kok Koh
2015	A*	`conf`	Construction of reconfigurable clock trees for MCMM designs. DAC Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh
2015	J	`jnl`	Cost-Effective Robustness in Clock Networks Using Near-Tree Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rickard Ewetz, Cheng-Kok Koh
2015	—	`conf`	Fast clock skew scheduling based on sparse-graph algorithms. ASP-DAC Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh
2015	A	`conf`	Human-pose estimation with neural-network realization. IROS Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee
2015	—	`conf`	Rubik: Unlocking the Power of Locality and End-point Flexibility in Cloud Scale Load Balancing. USENIX ATC Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh, Hongqiang Harry Liu, Ming Zhang
2014	J	`jnl`	A 3-D-Point-Cloud System for Human-Pose Estimation. IEEE Trans. Syst. Man Cybern. Syst. Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee
2014	—	`conf`	A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness. ACM Great Lakes Symposium on VLSI Rickard Ewetz, Anirudh Udupa, Ganesh Subbarayan, Cheng-Kok Koh
2014	—	`conf`	A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh
2014	—	`conf`	Analytical placement of mixed-size circuits for better detailed-routability. ASP-DAC Shuai Li, Cheng-Kok Koh
2014	J	`jnl`	Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cheng-Kok Koh, Chin Ngai Sze
2014	J	`jnl`	How to Improve Your Search Engine Ranking: Myths and Reality. ACM Trans. Web Ao-Jan Su, Y. Charlie Hu, Aleksandar Kuzmanovic, Cheng-Kok Koh
2014	—	`conf`	MIP-based detailed placer for mixed-size circuits. ISPD Shuai Li, Cheng-Kok Koh
2014	A*	`conf`	Selecting best viewpoint for human-pose estimation. ICRA Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee
2013	A*	`conf`	A 3D-point-cloud feature for human-pose estimation. ICRA Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee
2013	J	`jnl`	Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias. Microelectron. Reliab. Anirudh Udupa, Ganesh Subbarayan, Cheng-Kok Koh
2013	—	`conf`	Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. ISPD Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li
2013	—	`conf`	Collaborative object tracking with motion similarity measure. ROBIO Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee
2013	J	`jnl`	Guest editorial: Special section on cross-domain physical optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Cheng-Kok Koh
2013	—	`ed.`	International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013 ISPD Cheng-Kok Koh, Cliff C. N. Sze
2013	—	`conf`	Local merges for effective redundancy in clock networks. ISPD Rickard Ewetz, Cheng-Kok Koh
2013	J	`jnl`	On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM J. Emerg. Technol. Comput. Syst. Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh, Yaojun Zhang, Wujie Wen
2013	A*	`conf`	Optimization of placement solutions for routability. DAC Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li
2013	A	`conf`	Using action classification for human-pose estimation. IROS Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee
2012	J	`jnl`	A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao
2012	A	`conf`	A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. ICCAD Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh
2012	—	`conf`	A size scaling approach for mixed-size placement. ISPD Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan
2012	J	`jnl`	A two-dimensional domain decomposition technique for the simulation of quantum-scale devices. J. Comput. Phys. Stephen Cauley, Venkataramanan Balakrishnan, Gerhard Klimeck, Cheng-Kok Koh
2012	J	`jnl`	Guest Editorial Special Section on the 2011 International Symposium on Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Cheng-Kok Koh
2012	—	`ed.`	International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012 ISPD Jiang Hu, Cheng-Kok Koh
2012	—	`conf`	Mixed integer programming models for detailed placement. ISPD Shuai Li, Cheng-Kok Koh
2012	J	`jnl`	Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Guoyong Shi, Grantham K. H. Pang, Ngai Wong
2011	J	`jnl`	A parallel branch-and-cut approach for detailed placement. ACM Trans. Design Autom. Electr. Syst. Stephen Cauley, Venkataramanan Balakrishnan, Y. Charlie Hu, Cheng-Kok Koh
2011	—	`conf`	Cross link insertion for improving tolerance to variations in clock network synthesis. ISPD Tarun Mittal, Cheng-Kok Koh
2011	J	`jnl`	Finite difference schemes for heat conduction analysis in integrated circuit design and manufacturing. Int. J. Circuit Theory Appl. Yijiang Shen, Ngai Wong, Edmund Y. Lam, Cheng-Kok Koh
2011	A	`conf`	Processor caches with multi-level spin-transfer torque ram cells. ISLPED Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh
2011	—	`conf`	Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
2011	—	`conf`	Synthesis of low power clock trees for handling power-supply variations. ISPD Shashank Bujimalla, Cheng-Kok Koh
2010	J	`jnl`	A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephen Cauley, Venkataramanan Balakrishnan, Cheng-Kok Koh
2010	—	`conf`	How to Improve Your Google Ranking: Myths and Reality. Web Intelligence Ao-Jan Su, Y. Charlie Hu, Aleksandar Kuzmanovic, Cheng-Kok Koh
2010	J	`jnl`	Optimal Double Via Insertion With On-Track Preference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
2010	A	`conf`	PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. ICCAD Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong
2010	J	`jnl`	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy
2009	A*	`conf`	A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. DAC Wenwen Chai, Dan Jiao, Cheng-Kok Koh
2009	A	`conf`	A study of routability estimation and clustering in placement. ICCAD Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan
2009	J	`jnl`	Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. Very Large Scale Integr. Syst. Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
2009	C	`conf`	The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. ICCD Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li
2009	J	`jnl`	Tolerating process variations in large, set-associative caches: The buddy cache. ACM Trans. Archit. Code Optim. Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li
2008	C	`conf`	A fast band matching technique for impedance extraction. ISCAS Jitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan
2008	J	`jnl`	Fast and Optimal Redundant Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
2008	—	`ch.`	Global Interconnect Planning. Handbook of Algorithms for Physical Design Automation Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang
2008	A	`conf`	Guiding global placement with wire density. ICCAD Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan
2008	—	`conf`	Optimal post-routing redundant via insertion. ISPD Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
2007	A	`conf`	A fast band-matching technique for interconnect inductance modeling. ICCAD Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
2007	A	`conf`	A frequency-domain technique for statistical timing analysis of clock meshes. ICCAD Ruilin Wang, Cheng-Kok Koh
2007	J	`jnl`	Corrections to "Exact and Numerically Stable Closed-Form Expressions for Potential Coefficients of Rectangular Conductors". IEEE Trans. Circuits Syst. II Express Briefs Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
2007	—	`conf`	Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. ISQED Hong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh
2007	—	`conf`	Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. ISQED Chen Li, Cheng-Kok Koh
2007	J	`jnl`	Routability-Driven Placement and White Space Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden
2007	J	`jnl`	SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
2007	—	`conf`	Statistical Timing Analysis Considering Spatial Correlations. ISQED Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen
2007	C	`conf`	VOSCH: Voltage scaled cache hierarchies. ICCD Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li
2007	A	`conf`	Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
2006	—	`conf`	Adaptive admittance-based conductor meshing for interconnect analysis. ASP-DAC Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan
2006	—	`conf`	Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration. CICC Ruilin Wang, Cheng-Kok Koh, Byunghoo Jung, William J. Chappell
2006	J	`jnl`	Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors. IEEE Trans. Circuits Syst. II Express Briefs Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
2006	J	`jnl`	Performance analysis of latency-insensitive systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruibing Lu, Cheng-Kok Koh
2006	J	`jnl`	Postlayout optimization for synthesis of Domino circuits. ACM Trans. Design Autom. Electr. Syst. Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh
2006	—	`conf`	SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. ASP-DAC Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan
2006	—	`conf`	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2006	A	`conf`	Stable and compact inductance modeling of 3-D interconnect structures. ICCAD Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh
2006	J	`jnl`	Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, Tung-Sang Ng
2005	—	`conf`	3D module placement for congestion and power noise reduction. ACM Great Lakes Symposium on VLSI Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
2005	C	`conf`	A Performance and Power Co-optimization Approach for Modern Processors. CIT Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh
2005	A	`conf`	Cascaded carry-select adder (C ISLPED Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
2005	—	`conf`	Compact and stable modeling of partial inductance and reluctance matrices. ASP-DAC Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong
2005	J	`jnl`	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2005	—	`conf`	Floorplan management: incremental placement for gate sizing and buffer insertion. ASP-DAC Chen Li, Cheng-Kok Koh, Patrick H. Madden
2005	—	`conf`	Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies. CICC Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
2005	—	`conf`	Improving the scalability of SAMBA bus architecture. ASP-DAC Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
2005	J	`jnl`	Mixed block placement via fractional cut recursive bisection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ameya R. Agnihotri, Satoshi Ono, Chen Li, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden
2005	—	`conf`	Post-layout logic duplication for synthesis of domino circuits with complex gates. ASP-DAC Aiqun Cao, Ruibing Lu, Cheng-Kok Koh
2005	—	`conf`	Process variation robust clock tree routing. ASP-DAC Wai-Ching Douglas Lam, Cheng-Kok Koh
2005	A	`conf`	Statistical based link insertion for robust clock network design. ICCAD Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen
2005	J	`jnl`	Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2004	—	`conf`	A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction. ICASSP (5) Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, Tung-Sang Ng
2004	—	`conf`	A high performance bus communication architecture through bus splitting. ASP-DAC Ruibing Lu, Cheng-Kok Koh
2004	A	`conf`	Fast simulation of VLSI interconnects. ICCAD Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
2004	A*	`conf`	Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. DAC Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh
2004	A*	`conf`	Post-layout logic optimization of domino circuits. DAC Aiqun Cao, Cheng-Kok Koh
2004	—	`conf`	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2004	—	`conf`	Recursive bisection based mixed block placement. ISPD Ateen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden
2004	A	`conf`	Routability-driven placement and white space allocation. ICCAD Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden
2003	—	`conf`	A metric for analyzing effective on-chip inductive coupling. ASP-DAC Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2003	A*	`conf`	An adaptive window-based susceptance extraction and its efficient implementation. DAC Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy
2003	—	`conf`	Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. ISQED Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao
2003	—	`conf`	Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2003	A	`conf`	Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2003	A	`conf`	Interconnect Planning with Local Area Constrained Retiming. DATE Ruibing Lu, Cheng-Kok Koh
2003	C	`conf`	Non-Crossing OBDDs for Mapping to Regular Circuit Structures. ICCD Aiqun Cao, Cheng-Kok Koh
2003	J	`jnl`	On-chip interconnect modeling by wire duplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2003	A	`conf`	Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. ICCAD Ruibing Lu, Cheng-Kok Koh
2003	A	`conf`	SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. ICCAD Ruibing Lu, Cheng-Kok Koh
2002	A*	`conf`	A factorization-based framework for passivity-preserving model reduction of RLC systems. DAC Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
2002	J	`jnl`	Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2002	—	`conf`	Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. ASP-DAC/VLSI Design Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
2002	C	`conf`	Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. ICCD Guoan Zhong, Cheng-Kok Koh
2002	A	`conf`	Flip-Flop and Repeater Insertion for Early Interconnect Planning. DATE Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao
2002	A	`conf`	Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy
2002	A	`conf`	On-chip interconnect modeling by wire duplication. ICCAD Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2002	—	`conf`	Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. ASP-DAC/VLSI Design Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2002	—	`conf`	Power Supply Noise Suppression via Clock Skew Scheduling. ISQED Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao
2002	—	`conf`	Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2002	J	`jnl`	UST/DME: a clock tree router for general skew constraints. ACM Trans. Design Autom. Electr. Syst. Chung-Wen Albert Tsao, Cheng-Kok Koh
2001	—	`conf`	Decoupling capacitance allocation for power supply noise suppression. ISPD Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2001	C	`conf`	Efficient balance-and-truncate model reduction for large scale systems. ACC V. Balakrishnan, Q. Su, Cheng-Kok Koh
2001	A*	`conf`	Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2001	J	`jnl`	Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Cheng-Kok Koh, Patrick H. Madden
2001	J	`jnl`	Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
2001	—	`conf`	Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2001	—	`conf`	Power trends and performance characterization of 3-dimensional integration. ISCAS (4) Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2001	—	`ed.`	Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 ACM Great Lakes Symposium on VLSI Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh
2001	A	`conf`	Repeater block planning under simultaneous delay and transition time constraints. DATE Probir Sarkar, Cheng-Kok Koh
2001	J	`jnl`	Routability-driven repeater block planning for interconnect-centricfloorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Probir Sarkar, Cheng-Kok Koh
2001	A	`conf`	Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy
2001	—	`conf`	Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) Rui Wang, Kaushik Roy, Cheng-Kok Koh
2000	A	`conf`	A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2000	C	`conf`	Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2000	A	`conf`	Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2000	—	`conf`	Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. ACM Great Lakes Symposium on VLSI Cheng-Kok Koh, Patrick H. Madden
2000	—	`conf`	Power minimization by simultaneous dual-V CICC Liqiong Wei, Kaushik Roy, Cheng-Kok Koh
2000	—	`conf`	Routability-driven repeater block planning for interconnect-centric floorplanning. ISPD Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh
2000	C	`conf`	Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
2000	A	`conf`	Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2000	A	`conf`	UST/DME: A Clock Tree Router for General Skew Constraints. ICCAD Chung-Wen Albert Tsao, Cheng-Kok Koh
1998	J	`jnl`	Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
1997	A	`conf`	Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
1997	A	`conf`	Interconnect design for deep submicron ICs. ICCAD Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
1997	A	`conf`	Interconnect layout optimization under higher-order RLC model. ICCAD Jason Cong, Cheng-Kok Koh
1996	J	`jnl`	Performance optimization of VLSI interconnect layout. Integr. Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden
1996	A	`conf`	Simultaneous buffer and wire sizing for performance and power optimization. ISLPED Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
1995	A	`conf`	Bounded-skew clock and Steiner routing under Elmore delay. ICCAD Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
1995	C	`conf`	Minimum-Cost Bounded-Skew Clock Routing. ISCAS Jason Cong, Cheng-Kok Koh
1994	A	`conf`	Simultaneous driver and wire sizing for performance and power optimization. ICCAD Jason Cong, Cheng-Kok Koh
1994	J	`jnl`	Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Cheng-Kok Koh