Cheng-Hsiang Chiu

19 papers A* 2A 2B 1C 1Journal 2Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism.
ACM Trans. Design Autom. Electr. Syst.
Wan-Luan Lee, Dian-Lun Lin, Shui Jiang, Cheng-Hsiang Chiu, Yibo Lin, Bei Yu, Tsung-Yi Ho, Tsung-Wei Huang
2025 — conf
A Task-Parallel Pipeline Programming Model with Token Dependency.
WAMTA
Cheng-Hsiang Chiu, Wan-Luan Lee, Boyang Zhang, Yi-Hua Chung, Che Chang, Tsung-Wei Huang
2025 — conf
Enhancing Graph Partitioning with Reinforcement Learning-based Initialization.
HPEC
Chedi Morchdi, Cheng-Hsiang Chiu, Wan-Luan Lee, Tsung-Wei Huang, Yi Zhou
2025 — conf
HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner.
ASP-DAC
Wan-Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu, Ulf Schlichtmann, Tsung-Wei Huang
2025 — conf
Optimizing CUDA Graph Scheduling with Reinforcement Learning - A Case Study in SSTA Propagation.
MLCAD
Cheng-Hsiang Chiu, Chedi Morchdi, Chih-Chun Chang, Cunxi Yu, Yi Zhou, Tsung-Wei Huang
2025 — conf
PathGen: An Efficient Parallel Critical Path Generation Algorithm.
ASP-DAC
Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
2025 — conf
iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis.
ASP-DAC
Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
2024 B conf
A Resource-efficient Task Scheduling System using Reinforcement Learning : Invited Paper.
ASPDAC
Chedi Morchdi, Cheng-Hsiang Chiu, Yi Zhou, Tsung-Wei Huang
2024 C conf
An Efficient Task-Parallel Pipeline Programming Framework.
HPC Asia
Cheng-Hsiang Chiu, Zhicheng Xiong, Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2024 — conf
An Experimental Study of Dynamic Task Graph Parallelism for Large-Scale Circuit Analysis Workloads.
ISVLSI
Cheng-Hsiang Chiu, Tsung-Wei Huang
2024 A* conf
G-PASTA: GPU-Accelerated Partitioning Algorithm for Static Timing Analysis.
DAC
Boyang Zhang, Dian-Lun Lin, Che Chang, Cheng-Hsiang Chiu, Bojue Wang, Wan-Luan Lee, Chih-Chun Chang, Donghao Fang, Tsung-Wei Huang
2024 — conf
Incremental Critical Path Generation for Dynamic Graphs.
ISVLSI
Che Chang, Cheng-Hsiang Chiu, Boyang Zhang, Tsung-Wei Huang
2024 — conf
Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System.
ISPD
Tsung-Wei Huang, Boyang Zhang, Dian-Lun Lin, Cheng-Hsiang Chiu
2024 — conf
Reinforcement Learning-Generated Topological Order for Dynamic Task Graph Scheduling.
HPEC
Cheng-Hsiang Chiu, Chedi Morchdi, Yi Zhou, Boyang Zhang, Che Chang, Tsung-Wei Huang
2023 A conf
Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms.
ICCAD
Cheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang
2022 A conf
Composing Pipeline Parallelism using Control Taskflow Graph.
HPDC
Cheng-Hsiang Chiu, Tsung-Wei Huang
2022 A* conf
Efficient timing propagation with simultaneous structural and pipeline parallelisms: late breaking results.
DAC
Cheng-Hsiang Chiu, Tsung-Wei Huang
2022 J jnl
Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++.
CoRR
Cheng-Hsiang Chiu, Tsung-Wei Huang, Zizheng Guo, Yibo Lin
2021 — conf
An Experimental Study of SYCL Task Graph Parallelism for Large-Scale Machine Learning Workloads.
Euro-Par Workshops
Cheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang