Cheng-An Chien

18 papers C 5Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2014 — conf
A 360-degree panoramic video system design.
VLSI-DAT
Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo
2013 — conf
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.
ISSCC
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013 — conf
A view scalable multi-view video decoder system.
VLSI-DAT
Jui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo
2013 J jnl
Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization.
J. Signal Process. Syst.
Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo
2012 C conf
3D depth map generation for embedded stereo applications.
VCIP
Jui-Sheng Lee, Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo
2012 J jnl
A Verification-Aware Design Methodology for Thread Pipelining Parallelization.
IEICE Trans. Inf. Syst.
Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo
2012 C conf
A two level mode decision algorithm for H.264 high profile intra encoding.
ISCAS
Cheng-Yen Chang, Cheng-An Chien, Hsiu-Cheng Chang, Jia-Wei Chen, Jiun-In Guo
2012 — conf
An inter-frame/inter-view cache architecture design for multi-view video decoders.
APSIPA
Jui-Sheng Lee, Sheng-Han Wang, Chih-Tai Chou, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo
2012 J jnl
High efficiency data access system architecture for deblocking filter supporting multiple video coding standards.
IEEE Trans. Consumer Electron.
Cheng-An Chien, Guo-An Jian, Hsiu-Cheng Chang, Kuan-Hung Chen, Jiun-In Guo
2011 — conf
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
ASP-DAC
Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng
2011 — conf
A low-power management technique for high-performance domino circuits.
ASP-DAC
Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo
2011 — conf
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism.
ASP-DAC
Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo
2009 J jnl
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.
ACM Trans. Design Autom. Electr. Syst.
Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
2009 C conf
A Dynamic Quality-scalable H.264 Video Encoder.
ISCAS
Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo
2009 C conf
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards.
ISCAS
Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo
2009 C conf
A Multi-standard Video Decoder for High Definition Video Applications.
ISCAS
Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
2009 — conf
A dynamic quality-scalable H.264 video encoder chip.
ASP-DAC
Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang
2008 — conf
A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding.
APCCAS
Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo