Chen Yang - RankMe

58 papers A* 1A 1B 1C 1Journal 47Unranked 7

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Area-Efficient and Reconfigurable Accelerator for Massive MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. Siwei Xiang, Liyan Liang, Junfeng Wu, Jia Hou, Jiaxing Wang, Yishuo Meng, Jianfei Wang, Chen Yang
2026	J	`jnl`	BloomTree: A High-Throughput and Easily Scalable Packet Classifier on FPGA for Large-Scale Rulesets With Fast Online Rule Updates. IEEE Trans. Circuits Syst. I Regul. Pap. Zhijie Lin, Yunlei Qi, Maoquan Cai, Yishuo Meng, Jianfei Wang, Chen Yang
2026	J	`jnl`	STEED: Space and Time-Efficient Encrypted Database Using FHE. IEEE Trans. Dependable Secur. Comput. Fahong Zhang, Zhen Gu, Yiran Li, Yilei Wang, Cheng Hong, Zhaohui Chen, Yufei Wang, Yanheng Lu, Meng Li, Leibo Liu, Sheng Wang, Feifei Li, Chen Yang, Dimin Niu, Yuan Xie
2025	J	`jnl`	A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. IEEE Trans. Circuits Syst. II Express Briefs Jianfei Wang, Chen Yang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Leibo Liu
2025	J	`jnl`	A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow. IEEE Trans. Very Large Scale Integr. Syst. Yishuo Meng, Jianfei Wang, Qiang Fu, Jia Hou, Siwei Xiang, Ge Li, Chen Yang
2025	J	`jnl`	A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method. IEEE Trans. Circuits Syst. I Regul. Pap. Yishuo Meng, Junfeng Wu, Siwei Xiang, Jianfei Wang, Jia Hou, Zhijie Lin, Chen Yang
2025	J	`jnl`	A Mixed-Mode Acceleration via Sparsity-Adjustable Pruning for Balancing Computation Density in Lightweight CNNs. IEEE Trans. Very Large Scale Integr. Syst. Yishuo Meng, Qiang Fu, Jianfei Wang, Siwei Xiang, Jia Hou, Ge Li, Zhijie Lin, Chen Yang
2025	J	`jnl`	A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Jianfei Wang, Chen Yang, Yishuo Meng, Fahong Zhang, Jia Hou, Siwei Xiang, Yang Su
2025	J	`jnl`	A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. IEEE Trans. Very Large Scale Integr. Syst. Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang
2025	J	`jnl`	A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. IEEE Trans. Very Large Scale Integr. Syst. Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang
2025	J	`jnl`	A Self-Organizing Linked Storage Architecture With Dynamic Partition Achieving High Capacity Utilization. IEEE Trans. Circuits Syst. II Express Briefs Siwei Xiang, Yu Gao, Yishuo Meng, Jianfei Wang, Ge Li, Zhijie Lin, Chen Yang
2025	—	`conf`	A Unified Hardware Accelerator for Paillier and ElGamal with Masking and Improved Randomized Montgomery Ladder. AsianHOST Jianfei Wang, Zichu Liu, Jia Hou, Yishuo Meng, Zhijie Lin, Huansheng Shi, Maoquan Cai, Chen Yang
2025	J	`jnl`	An Efficient CNN Accelerator Exploiting Novel Tile-Based Near-Structured Sparsity to Achieve Multi-Level Irregularity Elimination. IEEE Trans. Circuits Syst. I Regul. Pap. Yishuo Meng, Chen Yang, Qiang Fu, Jianfei Wang, Siwei Xiang, Ge Li, Li Geng
2025	J	`jnl`	An Efficient Polynomial Multiplication Accelerator for Lattice-Based Cryptography With a 2-D Winograd-Based Divide-and-Conquer Method. IEEE Trans. Very Large Scale Integr. Syst. Jianfei Wang, Zhen Zhou, Fahong Zhang, Yishuo Meng, Jia Hou, Xin Tang, Chen Yang
2025	J	`jnl`	An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. IEEE Trans. Circuits Syst. II Express Briefs Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang
2025	—	`conf`	Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. ASP-DAC Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang
2025	J	`jnl`	PBSAcc: A High-Performance Hardware Accelerator for FHE With Improved Batch Programmable Bootstrapping. IEEE Trans. Circuits Syst. II Express Briefs Jianfei Wang, Fahong Zhang, Zhen Zhou, Yishuo Meng, Jia Hou, Xin Tang, Chen Yang
2025	J	`jnl`	RTA: A Reconfigurable Transformer Accelerator Exploiting Sparsity via Low-Bit-Width Prediction. IEEE Trans. Very Large Scale Integr. Syst. Yujie Chen, Chen Yang, Yuheng Xia, Yishuo Meng, Jianfei Wang, Qiang Fu, Li Geng
2025	J	`jnl`	Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Yishuo Meng, Jianfei Wang, Siwei Xiang, Jia Hou, Zhijie Lin, Kuizhi Mei, Chen Yang
2024	J	`jnl`	A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su
2024	J	`jnl`	A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. IEEE Trans. Circuits Syst. II Express Briefs Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su
2024	J	`jnl`	A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography. IEEE Trans. Circuits Syst. II Express Briefs Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang
2024	J	`jnl`	A Novel Two-Level Protection Scheme against Hardware Trojans on a Reconfigurable CNN Accelerator. Cryptogr. Zichu Liu, Jia Hou, Jianfei Wang, Chen Yang
2024	J	`jnl`	A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination. IEEE Trans. Circuits Syst. I Regul. Pap. Wenzheng He, Zikuo Lu, Xin Liu, Ziwei Xu, Jingshuo Zhang, Chen Yang, Li Geng
2024	J	`jnl`	ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach. IEEE Trans. Circuits Syst. II Express Briefs Yishuo Meng, Siwei Xiang, Jianfei Wang, Jia Hou, Chen Yang
2024	J	`jnl`	An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm. IEEE Trans. Inf. Forensics Secur. Fahong Zhang, Chen Yang, Rui Zong, Xinran Zheng, Jianfei Wang, Yishuo Meng
2024	J	`jnl`	Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Yang, Yaoyao Yang, Yishuo Meng, Kaibo Huo, Siwei Xiang, Jianfei Wang, Li Geng
2024	J	`jnl`	LSTM-CRP: Algorithm-Hardware Co-Design and Implementation of Cache Replacement Policy Using Long Short-Term Memory. Big Data Cogn. Comput. Yizhou Wang, Yishuo Meng, Jiaxing Wang, Chen Yang
2024	J	`jnl`	WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei
2023	J	`jnl`	A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access. IEEE Trans. Very Large Scale Integr. Syst. Chen Yang, Junfeng Wu, Siwei Xiang, Liyan Liang, Li Geng
2023	J	`jnl`	A Real-Time and Efficient Optical Flow Tracking Accelerator on FPGA Platform. IEEE Trans. Circuits Syst. I Regul. Pap. Yifan Gong, Jinshuo Zhang, Xin Liu, Jialin Li, Ying Lei, Zhe Zhang, Chen Yang, Li Geng
2023	J	`jnl`	An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow. IEEE Trans. Very Large Scale Integr. Syst. Yishuo Meng, Chen Yang, Siwei Xiang, Jianfei Wang, Kuizhi Mei, Li Geng
2023	—	`conf`	An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method. ICTA Yuheng Xia, Yishuo Meng, Siwei Xiang, Jianfei Wang, Chen Yang
2023	J	`jnl`	DRGN: a dynamically reconfigurable accelerator for graph neural networks. J. Ambient Intell. Humaniz. Comput. Chen Yang, Kaibo Huo, Long-Fei Geng, Kuizhi Mei
2023	J	`jnl`	POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection. Inf. Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang
2023	J	`jnl`	TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. IEEE Trans. Very Large Scale Integr. Syst. Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Yang Su
2022	C	`conf`	A Hardware Architecture of Feature Extraction for Real-Time Visual SLAM. IECON Jialin Li, Liangji Zhang, Xuewei Shen, Yifan Gong, Ying Lei, Chen Yang, Li Geng
2022	J	`jnl`	A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication. IEEE Trans. Very Large Scale Integr. Syst. Yang Su, Bai-Long Yang, Chen Yang, Zepeng Yang, Yi-Wei Liu
2022	J	`jnl`	A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers. IEEE Trans. Very Large Scale Integr. Syst. Chen Yang, Yishuo Meng, Kaibo Huo, Jiawei Xi, Kuizhi Mei
2022	J	`jnl`	RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks. J. Circuits Syst. Comput. Chen Yang, Jia Hou, Yizhou Wang, Haibo Zhang, Xiaoli Wang, Li Geng
2022	J	`jnl`	ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. Yang Su, Bai-Long Yang, Chen Yang, Songyin Zhao
2022	J	`jnl`	SDF-SLAM: A Deep Learning Based Highly Accurate SLAM Using Monocular Camera Aiming at Indoor Map Reconstruction With Semantic and Depth Fusion. IEEE Access Chen Yang, Qi Chen, Yaoyao Yang, Jingyu Zhang, Minshun Wu, Kuizhi Mei
2021	—	`conf`	A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference. ICECS Chen Yang, Zepeng Yang, Jia Hou, Yang Su
2021	J	`jnl`	High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor. J. Ambient Intell. Humaniz. Comput. Yang Su, Bai-Long Yang, Chen Yang, Jing-Yuan He
2021	J	`jnl`	UL-CNN: An Ultra-Lightweight Convolutional Neural Network Aiming at Flash-Based Computing-In-Memory Architecture for Pedestrian Recognition. J. Circuits Syst. Comput. Chen Yang, Jingyu Zhang, Qi Chen, Yi Xu, Cimang Lu
2020	J	`jnl`	A Stride-Based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. Chen Yang, Yizhou Wang, Xiaoli Wang, Li Geng
2020	—	`conf`	CRP: Context-directed Replacement Policy to Improve Cache Performance for Coarse-Grained Reconfigurable Arrays. ICECS Chen Yang, Jia Hou, Yizhou Wang, Li Geng
2020	J	`jnl`	FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption. IEEE Access Yang Su, Bailong Yang, Chen Yang, Luogeng Tian
2019	—	`conf`	A Fully Quantitative Scheme With Fine-grained Tuning Method For Lightweight CNN Acceleration. ICECS Chen Yang, Bowen Li, Yizhou Wang
2019	—	`conf`	CCP: Configuration Context based Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. ICECS Chen Yang, Jia Hou, Yizhou Wang, Qi Zhou, Li Geng
2019	J	`jnl`	WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Chen Yang, Yizhou Wang, Xiaoli Wang, Li Geng
2018	J	`jnl`	CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Leibo Liu, Chen Yang, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. IEEE Trans. Circuits Syst. II Express Briefs Leibo Liu, Zhaoshi Li, Chen Yang, Chenchen Deng, Shouyi Yin, Shaojun Wei
2017	J	`jnl`	CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. Chen Yang, Leibo Liu, Kai Luo, Shouyi Yin, Shaojun Wei
2016	A*	`conf`	Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. DAC Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei
2015	J	`jnl`	Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. J. Circuits Syst. Comput. Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei
2015	A	`conf`	Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). FPGA Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei
2014	B	`conf`	Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. FPL Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei