Chen Chen

16 papers A* 1Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2023 — conf
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography.
ASAP
Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han
2020 A* conf
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.
ISCA
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
2020 — conf
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.
Hot Chips Symposium
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
2018 J jnl
An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs.
IEICE Electron. Express
Yan He, Jianyi Meng, Zhijian Chen, Xiaoyan Xiang, Chen Chen
2017 J jnl
A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Sheng Wang, Chen Chen, Xiaoyan Xiang, Jian-Yi Meng
2017 — conf
A light-weight energy-efficient resilient circuit for variation tolerance.
ASICON
Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2017 J jnl
A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs.
IEICE Electron. Express
Sheng Wang, Chen Chen, Xiaoyan Xiang, Jianyi Meng
2017 — conf
A new error masking flip-flop with one cycle correction penalty.
ASICON
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2017 J jnl
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2017 J jnl
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor.
IEICE Electron. Express
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2016 J jnl
EDSU: Error detection and sampling unified flip-flop with ultra-low overhead.
IEICE Electron. Express
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan
2016 J jnl
TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor.
IEICE Electron. Express
Zhenqiang Yong, Xiaoyan Xiang, Jianyi Meng, Chen Chen
2016 J jnl
Value locality based storage compression memory architecture for ECG sensor node.
Sci. China Inf. Sci.
Chaojun Zhao, Chen Chen, Zhijian Chen, Jianyi Meng
2015 — conf
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction.
ASICON
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2015 — conf
A timing failure tolerance design with in-field simultaneous error detection and correction.
ASICON
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2015 — conf
An energy-efficient microprocessor using multilevel error correction for timing error tolerance.
ASICON
Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng