Chen-Yi Lee

243 papers A* 4A 4B 3C 31Misc 12Journal 103Unranked 86
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Programmable CMOS DEP Chip for Cell Manipulation.
IEEE Trans. Biomed. Circuits Syst.
Wen-Yue Lin, Lin-Hung Lai, Yi-Wei Lin, Chen-Yi Lee
2025 Misc conf
M*: On-Chip Microfluidic Operations With A-Star for Portable Diagnostics.
ICASSP
Cheng-Hsuan Hsieh, Eugene Lee, Peng Hsien Chi, Jiajie Diao, Chen-Yi Lee
2025 C conf
Multiple Sampling and Pixel-Wise Accumulation in CMOS Capacitive Sensor Array System for Real-Time Droplet Analysis.
ISCAS
Lin-Hung Lai, Wen-Yue Lin, Yu-Chen Hung, Yu-Hsian Wang, Hsi-Hao Huang, Chen-Yi Lee
2025 C conf
Smart Pattern Generation on Programmable Dielectrophoresis Array Chip for Single Particle Manipulation.
ISCAS
Yu-Hsiang Wang, Wen-Yue Lin, Lin-Hung Lai, Chen-Yi Lee
2024 C conf
A 2.56-µs Dynamic Range, 31.25-ps Resolution 2-D Vernier Digital-to-Time Converter (DTC) for Cell-Monitoring.
ISCAS
Heng-Yu Liu, Lin-Hung Lai, Wen-Yue Lin, Yu-Wei Lu, Yi-Wei Lin, Chen-Yi Lee
2024 J jnl
A Dual-Mode Readout Circuit for SPAD Imaging Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Hsi-Hao Huang, Tzu-Yun Huang, Chun-Hsien Liu, Sheng-Di Lin, Chen-Yi Lee
2024 J jnl
A Low-Latency Data Compressor for SPAD-Based Depth Estimation Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Tzu-Yun Huang, Po-Ya Huang, Chen-Yi Lee
2024 C conf
A Programmable CMOS Dielectrophoresis Array Chip with 128 × 128 Electrodes for Cell Manipulation.
ISCAS
Wen-Yue Lin, Lin-Hung Lai, Yi-Wei Lin, Chen-Yi Lee
2024 — conf
Industrial Semiconductor GPT: A Question-and-Answer System that Provides Professional Advice and Problem-Solving Methods for Semiconductor and Factory Equipment and Process.
ISIE
Yi-Cheng Yu, Cheng-Fu Liou, Shang-Wen Chuang, Chen-Yi Lee
2023 J jnl
A 460 800 Pixels CMOS Capacitive Sensor Array With Programmable Fusion Pixels and Noise Canceling for Life Science Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Lin-Hung Lai, Wen-Yue Lin, Yu-Wei Lu, Heng-Yu Lui, Shinsuke Yoshida, Shih-Hwa Chiou, Chen-Yi Lee
2023 C conf
A Pattern-Control Digital Microfluidic Bio-Chip for Fast Thermal Cycle in Nucleic Acid Amplification Tests.
ISCAS
Yun-Sheng Chan, Jiajie Diao, Chen-Yi Lee
2023 C conf
A Stack-Based In-Pixel Storage Circuit for SPAD Photon Counting.
ISCAS
Tzu-Yun Huang, Hsi-Hao Huang, Chun-Hsien Liu, Sheng-Di Lin, Chen-Yi Lee
2023 A conf
Cross-Resolution Flow Propagation for Foveated Video Super-Resolution.
WACV
Eugene Lee, Lien-Feng Hsu, Evan Chen, Chen-Yi Lee
2023 C conf
Self-Restoring and Low-Jitter Circuits for High Timing-Resolution SPAD Sensing Applications.
ISCAS
Hsi-Hao Huang, Chun-Hsien Liu, Tzu-Yun Huang, Sheng-Di Lin, Chen-Yi Lee
2022 J jnl
A Programmable Bio-Chip With Adaptive Pattern-Control Micro-Electrode-Dot-Array.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Sheng Chan, Chen-Yi Lee
2022 J jnl
A Traveling-Wave Dielectrophoresis Bio-Chip for Cell Manipulation in Standard CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Sheng Chan, Ting-Ting Hsu, Yi-Po Chen, Hsu-Min Wu, Yun-Ming Wang, Chen-Yi Lee
2022 — conf
Bio-Chips for Fast Medial Tests Networks.
VLSI-DAT
Chen-Yi Lee
2022 J jnl
Cross-Resolution Flow Propagation for Foveated Video Super-Resolution.
CoRR
Eugene Lee, Lien-Feng Hsu, Evan Chen, Chen-Yi Lee
2022 — conf
Fast Adaption for Multi Motor Anomaly Detection via Meta Learning and deep unsupervised learning.
ISIE
Yi-Cheng Yu, Shang-Wen Chuang, Hong-Han Shuai, Chen-Yi Lee
2021 A* conf
Few-Shot and Continual Learning with Attentive Independent Mechanisms.
ICCV
Eugene Lee, Cheng-Han Huang, Chen-Yi Lee
2021 J jnl
Few-Shot and Continual Learning with Attentive Independent Mechanisms.
CoRR
Eugene Lee, Cheng-Han Huang, Chen-Yi Lee
2020 J jnl
A Real-Time Wearable Assist System for Upper Extremity Throwing Action Based on Accelerometers.
Sensors
Kuang-Yow Lian, Wei-Hsiu Hsu, Deepak Balram, Chen-Yi Lee
2020 C conf
An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications.
ISCAS
Wei Chiang, Hsie-Chia Chang, Chen-Yi Lee
2020 J jnl
Convolutional neural networks for classification of music-listening EEG: comparing 1D convolutional kernels with 2D kernels and cerebral laterality of musical influence.
Neural Comput. Appl.
Kit Hwa Cheah, Humaira Nisar, Vooi Voon Yap, Chen-Yi Lee
2020 Misc conf
Cross-Domain Adaptation for Biometric Identification Using Photoplethysmogram.
ICASSP
Eugene Lee, Annie Ho, Yi-Ting Wang, Cheng-Han Huang, Chen-Yi Lee
2020 J jnl
FADE: Feature Aggregation for Depth Estimation With Multi-View Stereo.
IEEE Trans. Image Process.
Hsiao-Chien Yang, Po-Heng Chen, Kuan-Wen Chen, Chen-Yi Lee, Yong-Sheng Chen
2020 J jnl
Feature Consistency Training With JPEG Compressed Images.
IEEE Trans. Circuits Syst. Video Technol.
Sheng Wan, Tung-Yu Wu, Heng-Wei Hsu, Wing Hung Wong, Chen-Yi Lee
2020 J jnl
Meta-rPPG: Remote Heart Rate Estimation Using a Transductive Meta-Learner.
CoRR
Eugene Lee, Evan Chen, Chen-Yi Lee
2020 — conf
Meta-rPPG: Remote Heart Rate Estimation Using a Transductive Meta-learner.
ECCV (27)
Eugene Lee, Evan Chen, Chen-Yi Lee
2020 — conf
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals.
EMBC
Yi-Hui Wu, Yi-Huan Ou-Yang, Chiung-Chu Chen, Chen-Yi Lee, Chung-Yu Wu, Ming-Dou Ker
2020 J jnl
Multitarget Sample Preparation Using MEDA Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee
2020 A* conf
NeuralScale: Efficient Scaling of Neurons for Resource-Constrained Deep Neural Networks.
CVPR
Eugene Lee, Chen-Yi Lee
2020 J jnl
NeuralScale: Efficient Scaling of Neurons for Resource-Constrained Deep Neural Networks.
CoRR
Eugene Lee, Chen-Yi Lee
2019 — conf
A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR.
VLSI-DAT
Yun-Wen Lu, Antoon Purnal, Simon Vandenhende, Chen-Yi Lee, Ingrid Verbauwhede, Hsie-Chia Chang
2019 C conf
Centralized State Sensing using Sensor Array on Wearable Device.
ISCAS
Eugene Lee, Tsu-Jui Hsu, Chen-Yi Lee
2019 C conf
Joint Capacitive Sensing and Frequency Selection for Fast Medical Tests.
ISCAS
Yun-Sheng Chan, Kuan-Yu Lung, Yun-Ming Wang, Chen-Yi Lee
2019 J jnl
Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques.
IEEE Trans. Biomed. Circuits Syst.
Zhanwei Zhong, Zipeng Li, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee
2019 J jnl
QuatNet: Quaternion-Based Head Pose Estimation With Multiregression Loss.
IEEE Trans. Multim.
Heng-Wei Hsu, Tung-Yu Wu, Sheng Wan, Wing Hung Wong, Chen-Yi Lee
2019 — conf
Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips.
ASP-DAC
Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee
2019 — conf
Short-time-span EEG-based personalized emotion recognition with deep convolutional neural network.
ICSIPA
Kit Hwa Cheah, Humaira Nisar, Vooi Voon Yap, Chen-Yi Lee
2018 — conf
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS.
VLSI-DAT
Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee
2018 J jnl
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits
Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu
2018 Misc conf
Confnet: Predict with Confidence.
ICASSP
Sheng Wan, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee
2018 Misc conf
Correlation-Based Face Detection for Recognizing Faces in Videos.
ICASSP
Heng-Wei Hsu, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee
2018 Misc conf
Diabetic Retinopathy Detection Based on Deep Convolutional Neural Networks.
ICASSP
Yi-Wei Chen, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee
2018 J jnl
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zipeng Li, Kelvin Yi-Tse Lai, John McCrone, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee
2018 J jnl
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee
2017 J jnl
A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications.
IEEE J. Solid State Circuits
Chang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee
2017 J jnl
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Szu-Chi Chung, Chun-Yuan Yu, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee
2017 — conf
Design considerations and clinical applications of closed-loop neural disorder control SoCs.
ASP-DAC
Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw
2017 J jnl
Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst.
Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee
2017 J jnl
Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst.
Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee
2017 — conf
Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
ISVLSI
Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee
2016 — conf
A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications.
A-SSCC
Chang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee
2016 — conf
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.
A-SSCC
Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2016 J jnl
A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Yingchieh Ho, Shu-Yu Hsu, Chen-Yi Lee
2016 J jnl
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2016 A conf
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips.
ITC
Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee
2016 C conf
Design of a micro-electrode cell for programmable lab-on-CMOS platform.
ISCAS
Yingchieh Ho, Gary Wang, Kelvin Yi-Tse Lai, Yi-Wen Lu, Keng-Ming Liu, Yun-Ming Wang, Chen-Yi Lee
2016 A conf
Error recovery in a micro-electrode-dot-array digital microfluidic biochip?
ICCAD
Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee
2016 A* conf
High-level synthesis for micro-electrode-dot-array digital microfluidic biochips.
DAC
Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee
2015 — conf
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.
ESSCIRC
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 C conf
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.
ISCAS
Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System.
IEEE Trans. Circuits Syst. II Express Briefs
Chang-Hung Tsai, Yu-Ting Chih, Wing Hung Wong, Chen-Yi Lee
2015 — conf
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process.
A-SSCC
Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
An Intelligent Digital Microfluidic Processor for Biomedical Detection.
J. Signal Process. Syst.
Kelvin Yi-Tse Lai, Yu-Tao Yang, Chen-Yi Lee
2015 J jnl
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability.
IEEE Trans. Very Large Scale Integr. Syst.
Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2015 — conf
An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver.
VLSI-DAT
Ping-Yuan Tsai, Yu-Yun Chang, Shu-Yu Hsu, Chen-Yi Lee
2015 J jnl
Efficient Hardware Architecture of η
IEEE Trans. Very Large Scale Integr. Syst.
Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.
A-SSCC
Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee
2014 C conf
A 2 GOPS quad-mean shift processor with early termination for machine learning applications.
ISCAS
Chang-Hung Tsai, Hui-Hsuan Lee, Wan-Ju Yu, Chen-Yi Lee
2014 J jnl
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring.
A-SSCC
Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee
2014 J jnl
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications.
IEEE J. Solid State Circuits
Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee
2014 — conf
A 7.11mJ/Gb/query data-driven machine learning processor (D
VLSIC
Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee
2014 C conf
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.
ISCAS
Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2014 J jnl
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
Event-driven read-out circuits for energy-efficient sensor-SoC's.
VLSI-DAT
Chen-Yi Lee, Kelvin Yi-Tse Lai, Shu-Yu Hsu
2014 — conf
What is a good way to expand a silicon value to a solution value?
A-SSCC
Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara
2013 — conf
A digital microfluidic processor for biomedical applications.
SiPS
Kelvin Yi-Tse Lai, Yu-Tao Yang, Gary Wang, Yi-Wen Lu, Chen-Yi Lee
2013 J jnl
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2013 — conf
Processor with side-channel attack resistance.
ISSCC
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
2013 J jnl
Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan.
IEEE Access
Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang
2012 J jnl
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.
IEEE J. Solid State Circuits
Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee
2012 — conf
A 4.88µW ECG delineator using wavelet transform for mobile healthcare application.
BioCAS
Po-Yao Chang, Shu-Yu Hsu, Chen-Yi Lee
2012 J jnl
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits
Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2012 J jnl
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee
2012 J jnl
A Low-Power DCO Using Interlaced Hysteresis Delay Cells.
IEEE Trans. Circuits Syst. II Express Briefs
Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, Chen-Yi Lee
2012 J jnl
A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine.
IEEE Trans. Circuits Syst. II Express Briefs
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2012 C conf
A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance.
ISCAS
Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee
2012 — conf
A low cost DPA-resistant 8-bit AES core based on ring oscillators.
VLSI-DAT
Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2012 — conf
A memory-efficient architecture for intra predictor and de-blocking filter in video coding system.
APCCAS
Chia-Lin Liu, Chang-Hung Tsai, Hsiuan-Ting Wang, Yao Li, Chen-Yi Lee
2012 — conf
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications.
VLSIC
Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee
2012 A conf
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor.
CHES
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
2012 J jnl
An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor.
IEEE Trans. Circuits Syst. II Express Briefs
Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
2012 C conf
Extrinsic data compression method for double-binary turbo codes.
ISCAS
Yi-Huan Ou-Yang, Chien-Yu Kao, Jen-Yuan Hsu, Pangan Ting, Chen-Yi Lee
2012 — conf
Spatial Isolation on Realtime Hypervisor using Core-local Memory.
PECCS
Daisuke Yamaguchi, Takumi Yajima, Chen-Yi Lee, Hiromasa Shimada, Yuki Kinebuchi, Tatsuo Nakajima
2012 C conf
Stochastic decoding for LDPC convolutional codes.
ISCAS
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2011 — conf
A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications.
A-SSCC
Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee
2011 — conf
A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems.
ESSCIRC
Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2011 — conf
A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence.
ESSCIRC
Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
2011 J jnl
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications.
J. Signal Process. Syst.
Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, Chen-Yi Lee
2011 J jnl
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2011 J jnl
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.
IEEE Trans. Circuits Syst. II Express Briefs
Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
2011 J jnl
A Predefined Bit-Plane Comparison Coding for Mobile Video Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Chien-Chen Lin, Yao Li, Chen-Yi Lee
2011 J jnl
A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Wei-Hao Sung, Jui-Yuan Yu, Chen-Yi Lee
2011 J jnl
A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters.
IEEE J. Solid State Circuits
Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee
2011 C conf
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit.
ISCAS
Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2011 — conf
A low power all-digital signal component separator for uneven multi-level LINC systems.
ESSCIRC
Tsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, Jui-Yuan Yu, Chen-Yi Lee
2011 — conf
A low-power all-digital phase modulator pair for LINC transmitters.
SoCC
Ping-Yuan Tsai, Tsan-Wen Chen, Chen-Yi Lee
2011 — conf
A micropower biomedical signal processor for mobile healthcare applications.
A-SSCC
Shu-Yu Hsu, Yao-Lin Chen, Po-Yao Chang, Jui-Yuan Yu, Ten-Fang Yang, Ray-Jade Chen, Chen-Yi Lee
2011 C conf
An area-efficient high-accuracy prediction-based CABAC decoder architecture for H.264/AVC.
ISCAS
Ming-Yu Kuo, Yao Li, Chen-Yi Lee
2011 — conf
An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications.
SoCC
Tzu-Chun Shih, Tsan-Wen Chen, Wei-Hao Sung, Ping-Yuan Tsai, Chen-Yi Lee
2011 C conf
Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design.
ISORC
Tsung-Han Lin, Yuki Kinebuchi, Alexandre Courbot, Hiromasa Shimada, Takushi Morita, Hitoshi Mitake, Chen-Yi Lee, Tatsuo Nakajima
2011 — conf
Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design.
RTCSA (2)
Tsung-Han Lin, Yuki Kinebuchi, Hiromasa Shimada, Hitoshi Mitake, Chen-Yi Lee, Tatsuo Nakajima
2010 J jnl
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.
IEEE J. Solid State Circuits
Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2010 — conf
A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance.
ESSCIRC
Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee
2010 J jnl
A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors.
IEEE Trans. Circuits Syst. II Express Briefs
Chen-Fong Hsiao, Yuan Chen, Chen-Yi Lee
2010 J jnl
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2010 J jnl
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.
J. Low Power Electron.
Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang
2010 J jnl
A Sub-10-muhboxW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Shu-Yu Hsu, Jui-Yuan Yu, Chen-Yi Lee
2010 — conf
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique.
APCCAS
Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee
2010 C conf
An improved soft BCH decoder with one extra error compensation.
ISCAS
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2010 J jnl
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications.
IEICE Electron. Express
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2010 — conf
Tunable magnetic alginate microspheres by using a microfluidic device.
NEMS
Chen-Yi Lee, Song-Bin Huang, Kang-Yi Lien, Ming-Yang Lin, Gwo-Bin Lee
2010 J jnl
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
IEEE J. Solid State Circuits
Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
2009 J jnl
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications.
IEEE J. Solid State Circuits
Tsan-Wen Chen, Jui-Yuan Yu, Chien-Ying Yu, Chen-Yi Lee
2009 — conf
A 0.92mm
CICC
Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2009 — conf
A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit.
ESSCIRC
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2009 — conf
A 11.5-Gbps LDPC decoder based on CP-PEG code construction.
ESSCIRC
Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee
2009 J jnl
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee
2009 C conf
An eCrystal Oscillator with Self-calibration Capability.
ISCAS
Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee
2009 J jnl
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2009 C conf
Design of an Intra Predictor with Data Reuse for High-profile H.264 Applications.
ISCAS
Yu-Fan Lai, Tsu-Ming Liu, Yao Li, Chen-Yi Lee
2008 J jnl
A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems.
IEEE J. Solid State Circuits
Yuan Chen, Yu-Wei Lin, Yu-Chi Tsao, Chen-Yi Lee
2008 J jnl
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Jui-Yuan Yu, Ching-Che Chung, Chen-Yi Lee
2008 J jnl
An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan Chen, Yu-Chi Tsao, Yu-Wei Lin, Chin-Hung Lin, Chen-Yi Lee
2008 J jnl
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.
IEEE J. Solid State Circuits
Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 — conf
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications.
APCCAS
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2008 — conf
Design of a memory-based VLC decoder for portable video applications.
APCCAS
Wei-Chin Lee, Yao Li, Chen-Yi Lee
2008 J jnl
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead.
J. Signal Process. Syst.
Tsu-Ming Liu, Chen-Yi Lee
2008 C conf
Multi-mode message passing switch networks applied for QC-LDPC decoder.
ISCAS
Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua
2007 — conf
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.
CICC
Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su
2007 J jnl
A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications.
IEEE J. Solid State Circuits
Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Jiun-Yan Yang, Kang-Cheng Hou, Chen-Yi Lee
2007 J jnl
A New Soft Variable Length Decoder for Wireless Video Transmission.
IEEE Trans. Circuits Syst. Video Technol.
Tsu-Ming Liu, Sheng-Zen Wang, Bai-Jue Shieh, Chen-Yi Lee
2007 — conf
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications.
ISSCC
Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee
2007 J jnl
An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule.
IEEE Trans. Circuits Syst. Video Technol.
Tsu-Ming Liu, Wen-Ping Lee, Chen-Yi Lee
2007 J jnl
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2007 — conf
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems.
SoCC
Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, Chen-Yi Lee
2007 J jnl
Design of a DVB-T/H COFDM Receiver for Portable Video Applications [Topics in Circuits for Communications].
IEEE Commun. Mag.
Lei-Fone Chen, Chen-Yi Lee
2007 J jnl
Design of an FFT/IFFT Processor for MIMO OFDM Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu-Wei Lin, Chen-Yi Lee
2007 J jnl
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Terng-Ren Hsu, Chien-Ching Lin, Terng-Yin Hsu, Chen-Yi Lee
2006 — conf
A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications.
ISSCC
Lei-Fone Chen, Yuan Chen, Lu-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee
2006 — conf
A 125µw, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications.
ISSCC
Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang, Chen-Yi Lee
2006 J jnl
A Context Adaptive Bit-Plane Coder With Maximum-Likelihood-Based Stochastic Bit-Reshuffling Technique for Scalable Video Coding.
IEEE Trans. Multim.
Wen-Hsiao Peng, Tihao Chiang, Hsueh-Ming Hang, Chen-Yi Lee
2006 — conf
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications.
APCCAS
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2006 J jnl
A Low-Complexity Synchronizer for OFDM-Based UWB System.
IEEE Trans. Circuits Syst. II Express Briefs
Hsuan-Yu Liu, Chen-Yi Lee
2006 — conf
A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System.
APCCAS
Shao-Ming Sun, Tsu-Ming Liu, Chen-Yi Lee
2006 J jnl
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications.
IEEE J. Solid State Circuits
Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee
2006 J jnl
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2006 J jnl
A low-power dual-mode video decoder for mobile applications.
IEEE Commun. Mag.
Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Chen-Yi Lee
2006 — conf
An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications.
APCCAS
Tsu-Ming Liu, Chen-Yi Lee
2006 A* conf
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications.
DAC
Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang
2005 J jnl
A 1-GS/s FFT/IFFT processor for UWB applications.
IEEE J. Solid State Circuits
Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee
2005 — conf
A 3.33Gb/s (1200,720) low-density parity check code decoder.
ESSCIRC
Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee
2005 J jnl
A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pao-Lung Chen, Chen-Yi Lee
2005 — conf
A memory-efficient deblocking filter for H.264/AVC video coding.
ISCAS (3)
Tsu-Ming Liu, Wen-Ping Lee, Ting-An Lin, Chen-Yi Lee
2005 — conf
A new motion compensation design for H.264/AVC decoder.
ISCAS (5)
Sheng-Zen Wang, Ting-An Lin, Tsu-Ming Liu, Chen-Yi Lee
2005 — conf
A novel technique for I/Q imbalance and CFO compensation in OFDM systems.
ISCAS (6)
Jui-Yuan Yu, Ming-Fu Sun, Terng-Yin Hsu, Chen-Yi Lee
2005 J jnl
A portable digitally controlled oscillator using novel varactors.
IEEE Trans. Circuits Syst. II Express Briefs
Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
2005 — conf
An H.264/AVC decoder with 4×4-block level pipeline.
ISCAS (2)
Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee
2005 — conf
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications.
ISCAS (5)
Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
2005 — conf
An area-efficient and high-throughput de-blocking filter for multi-standard video applications.
ICIP (3)
Tsu-Ming Liu, Wen-Ping Lee, Chen-Yi Lee
2005 J jnl
Design of a power-reduction Viterbi decoder for WLAN applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2005 J jnl
Guest Editorial: System-on-a-Chip for Multimedia Systems.
J. VLSI Signal Process.
Yen-Kuang Chen, Stella Kuei-Ann Wen, Chen-Yi Lee
2005 — conf
Predictive equalizer design for DVB-T system.
ISCAS (2)
Ting-An Lin, Chen-Yi Lee
2004 — conf
A dual mode channel decoder for 3GPP2 mobile wireless communications.
ESSCIRC
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2004 J jnl
A dynamic scaling FFT processor for DVB-T applications.
IEEE J. Solid State Circuits
Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee
2004 B conf
A low-complexity soft vlc decoder using performance modeling.
ICIP
Tsu-Ming Liu, Chen-Yi Lee
2004 — conf
A low-power group-based VLD design.
ISCAS (2)
Cheng-Hung Liu, Bai-Jue Shieh, Chen-Yi Lee
2004 J jnl
A new DLL-based approach for all-digital multiphase clock generation.
IEEE J. Solid State Circuits
Ching-Che Chung, Chen-Yi Lee
2004 — conf
A power and area efficient multi-mode FEC processor.
ISCAS (2)
Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
2004 — conf
Enhanced Stochastic Bit Reshuffling for Fine Granular Scalable Video Coding.
PCM (2)
Wen-Hsiao Peng, Tihao Chiang, Hsueh-Ming Hang, Chen-Yi Lee
2003 — conf
A Design of CMOS Broadband Amplifier With High-Q Active Inductor.
IWSOC
Jhy-Neng Yang, Yi-Chang Cheng, Chen-Yi Lee
2003 J jnl
A Low-Power Design for Reed-Solomon Decoders.
J. Circuits Syst. Comput.
Hsie-Chia Chang, Chen-Yi Lee
2003 — conf
A low power and high speed Viterbi decoder chip for WLAN applications.
ESSCIRC
Chien-Ching Lin, Chia-Cho Wu, Chen-Yi Lee
2003 J jnl
An all-digital phase-locked loop for high-speed clock generation.
IEEE J. Solid State Circuits
Ching-Che Chung, Chen-Yi Lee
2003 — conf
Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems.
ISCAS (2)
Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Jen Hung, Temg-Yin Hsu, Chen-Yi Lee
2003 J jnl
Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission.
IEEE Trans. Circuits Syst. Video Technol.
Yew-San Lee, Keng-Khai Ong, Chen-Yi Lee
2003 — conf
Infrastructure for Education and Research of SOC/IP in Taiwan.
MSE
Wei-Chang Tsai, Chun-Ming Huang, Jiann-Jenn Wang, Chen-Yi Lee
2003 J jnl
Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware.
Vis. Comput.
Cheng-Hsien Chen, Chen-Yi Lee
2002 J jnl
A JPEG-like texture compression with adaptive quantization for 3D graphics application.
Vis. Comput.
Cheng-Hsien Chen, Chen-Yi Lee
2002 — conf
A high throughput context-based adaptive arithmetic codec for JPEG2000.
ISCAS (4)
Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee
2002 — conf
A high throughput low cost context-based adaptive arithmetic codec for multiple standards.
ICIP (1)
Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee
2002 Misc conf
A novel DCT-based bit plane error resilient entropy coding for wireless multimedia communication.
ICASSP
Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee
2002 — conf
A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication.
ISCAS (5)
Yew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, Chen-Yi Lee
2002 — conf
A novel fixed bit plane error resilient image coding for wireless multimedia transmission.
ICIP (3)
Hung-Kuo Wei, Yew-San Lee, Yen-Hsu Shih, Chen-Yi Lee
2002 J jnl
Design of a wide-band frequency synthesizer based on TDC and DVC techniques.
IEEE J. Solid State Circuits
Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang, Yi-Chuan Liu, Chen-Yi Lee
2002 Misc conf
Error resilient image coding and smart post-processing error concealment for wireless image transmission.
ICASSP
Keng-Khai Ong, Yew-San Lee, Chen-Yi Lee
2002 — conf
FPGA education and research activities in Taiwan.
FPT
Yu-Tsang Chang, Yu-Te Chou, Wei-Chang Tsai, Jiann-Jenn Wang, Chen-Yi Lee
2002 J jnl
Reduce the Memory Bandwidth of 3D Graphics Hardware with a Novel Rasterizer.
J. Circuits Syst. Comput.
Cheng-Hsien Chen, Chen-Yi Lee
2001 J jnl
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications.
IEEE J. Solid State Circuits
Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee
2001 — conf
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme.
ISCAS (4)
Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee
2001 J jnl
A new approach of group-based VLC codec system with full table programmability.
IEEE Trans. Circuits Syst. Video Technol.
Bai-Jue Shieh, Yew-San Lee, Chen-Yi Lee
2001 — conf
A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system.
ISCAS (4)
Frank S. Tsai, Chen-Yi Lee
2001 — conf
A novel structure for portable digitally controlled oscillator.
ISCAS (1)
Jin-Jer Jong, Chen-Yi Lee
2001 — conf
A novel subcircuit extraction algorithm by recursive identification scheme.
ISCAS (5)
Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee
2001 — conf
A wideband digital frequency synthesizer.
ISCAS (4)
Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee
2001 — conf
An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm.
ISCAS (2)
Hsie-Chia Chang, Chen-Yi Lee
2001 — conf
Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission.
ISCAS (4)
Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee
2000 J jnl
A high-throughput memory-based VLC decoder with codeword boundary prediction.
IEEE Trans. Circuits Syst. Video Technol.
Bai-Jue Shieh, Yew-San Lee, Chen-Yi Lee
2000 C conf
A new approach of group-based VLC codec system.
ISCAS
Bai-Jue Shieh, Terng-Yin Hsu, Chen-Yi Lee
2000 B conf
Construction of Error Resilient Synchronization Codeword for Variable-Length Code in Image Transmission.
ICIP
Yew-San Lee, Wei-Shin Chang, Hsin-Han Ho, Chen-Yi Lee
2000 — conf
FORTE-VLC: A forward tracing self-error correction variable length code for image coding in wireless application.
EUSIPCO
Yew-San Lee, Keng-Khai Ong, Wei-Shin Chang, Chen-Yi Lee
2000 Misc conf
HVLC: error correctable hybrid variable length code for image coding in wireless transmission.
ICASSP
Yew-San Lee, Cheng-Mou Yu, Wei-Shin Chang, Chen-Yi Lee
1999 — conf
A Cost-Effective Lighting Processor for 3D Graphics Application.
ICIP (2)
Cheng-Hsien Chen, Chen-Yi Lee
1999 — conf
A New Anti-Aliasing Algorithm for Computer Graphics Images.
ICIP (2)
Yuan-Hau Yeh, Chen-Yi Lee
1999 — conf
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform.
ICIP (2)
Wen-Shiaw Peng, Chen-Yi Lee
1999 J jnl
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit.
IEEE J. Solid State Circuits
Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee
1999 Misc conf
An efficient VLC decompression scheme for user-defined coding tables.
ICASSP
Bai-Jue Shieh, Chen-Yi Lee
1999 J jnl
Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Hau Yeh, Chen-Yi Lee
1998 Misc conf
Entropy-constrained gradient-match vector quantization for image coding.
ICASSP
Shin-Chou Juan, Chen-Yi Lee
1997 J jnl
A multicasting solution for ATM video applications.
IEEE Trans. Circuits Syst. Video Technol.
Jer-Min Tsai, Hsin-Hsiung Fang, Chen-Yi Lee
1997 J jnl
An Efficient VLSI Architecture for Full-Search Block Matching Algorithms.
J. VLSI Signal Process.
Chen-Yi Lee, Mei-Cheng Lu
1997 — conf
Buffer size optimization for full-search block matching algorithms.
ASAP
Yuan-Hau Yeh, Chen-Yi Lee
1996 J jnl
Finite state vector quantization with multipath tree search strategy for image/video coding.
IEEE Trans. Circuits Syst. Video Technol.
Chen-Yi Lee, Shih-Chou Juan, Yen-Juan Chao
1996 — conf
Scalable VLSI architectures for full-search block matching algorithms.
ICIP (2)
Yuan-Hau Yeh, Chen-Yi Lee
1996 B conf
The outage probability in DS/CDMA for cellular mobile radio with imperfect power control.
PIMRC
Terng-Yin Hsu, Chen-Yi Lee
1995 C conf
A New Multi-Path Tree-Search FSVQ Architecture for Image/Video Sequence Coding.
ISCAS
Yen-Juan Chao, Chen-Yi Lee
1995 J jnl
A shift register architecture for high-speed data sorting.
J. VLSI Signal Process.
Chen-Yi Lee, Jer-Min Tsai
1995 C conf
An Efficient Memory Architecture for Motion Estimation Processor Design.
ISCAS
Eddie G. Tzeng, Chen-Yi Lee
1995 Misc conf
Semi-systolic array based motion estimation processor design.
ICASSP
Mei-Cheng Lu, Chen-Yi Lee
1994 C conf
Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy.
ISCAS
Wen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee
1994 C conf
Finite State Vector Quantization with Multi-Path Tree Search Strategy for Image/Video Coding.
ISCAS
Shih-Chou Juan, Yen-Jean Chao, Chen-Yi Lee
1994 C conf
High-Throughput Data Compressor Designs Using Content Addressable Memory.
ISCAS
Ren-Yang Yang, Chen-Yi Lee
1994 J jnl
High-speed median filter designs using shiftable content-addressable memory.
IEEE Trans. Circuits Syst. Video Technol.
Chen-Yi Lee, Po-Wen Hsieh, Jer-Min Tsai
1993 C conf
An area-efficient maximum/minimum detection circuit for digital and video signal processing.
ISCAS
Chen-Yi Lee, Shih-Chou Juan, Wen-Wei Yang
1993 J jnl
VLSI implementation of an M-array image filter based on shift register array.
Integr.
Chen-Yi Lee, Jer-Min Tsai, Shih-Chieh Hsu
1991 Misc conf
Breaking the bottleneck of sequential decoding for high-speed digital communication.
ICASSP
Chen-Yi Lee, Francky Catthoor, Hugo De Man
1990 J jnl
Efficient VLSI Architectures for a High-Performance Digital Image Communication System.
IEEE J. Sel. Areas Commun.
Chen-Yi Lee, Francky Catthoor, Hugo De Man