| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2011 | A | conf |
DATE
|
| 2011 | — | conf |
SLIP
|
| 2010 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2010 | A* | conf |
DAC
|
| 2010 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2009 | A | conf |
DATE
|
| 2008 | C | conf |
ICCD
|
| 2008 | J | jnl |
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2008 | A | conf |
DATE
|
| 2007 | Misc | conf |
CODES+ISSS
|
| 2004 | C | conf |
ICCD
|