Chen-Huan Chiang

15 papers A 8Misc 2Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2011 Misc conf
Design for Bit Error Rate estimation of high speed serial links.
VTS
Ujjwal Guin, Chen-Huan Chiang
2010 J jnl
A Common Language Framework for Next-Generation Embedded Testing.
IEEE Des. Test Comput.
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
2008 A conf
A New Language Approach for IJTAG.
ITC
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
2008 A conf
Problems Using Boundary-Scan for Memory Cluster Tests.
ITC
Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker
2007 A conf
A practical approach to comprehensive system test & debug using boundary scan based test architecture.
ITC
Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren
2007 — conf
FPGA Prototyping of a Scan Based System-On-Chip Design.
ReCoSoC
Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook
2004 A conf
Testing and Remote Field Update of Distributed Base Stations in a Wireless Network.
ITC
Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung
2002 A conf
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.
ITC
Tapan J. Chakraborty, Chen-Huan Chiang
2000 J jnl
BIST TPG for Combinational Cluster Interconnect Testing at Board Level.
J. Electron. Test.
Chen-Huan Chiang, Sandeep K. Gupta
2000 — conf
BIST TPG for SRAM cluster interconnect testing at board level.
Asian Test Symposium
Chen-Huan Chiang, Sandeep K. Gupta
2000 A conf
End-to-end testing for boards and systems using boundary scan.
ITC
Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace
1998 — conf
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level.
Asian Test Symposium
Chen-Huan Chiang, Sandeep K. Gupta
1997 A conf
BIST TPG for faults in system backplanes.
ICCAD
Chen-Huan Chiang, Sandeep K. Gupta
1997 Misc conf
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.
VTS
Chen-Huan Chiang, Sandeep K. Gupta
1994 A conf
Random pattern testable logic synthesis.
ICCAD
Chen-Huan Chiang, Sandeep K. Gupta